[ImportVerilog] Add foreach statement support. #8017
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Maybe you can refer to the implementation of Handle repeat loops. We can pass the cond to the BB1 when we enter. I guess this method can reduce accessing memory(like read and blokcing_assign ops) frequently 🤔. WDYT @fabianschuiki?
hailongSun2000
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hailongSun2000
approved these changes
Dec 30, 2024
fabianschuiki
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Jan 9, 2025
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Looks great, thanks for the fix! Feel free to land this whenever you're happy with it 😃. Or let me know if you want me to do it. |
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Add forloop statement support, due to lack of dyn array support, currently static-length array is supported.