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[ImportVerilog] Support for Procedural assign statements #8010

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[ImportVerilog] Support for Procedural assign statements #8010

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[ImportVerilog] Support for Procedural assign statements
owlxiao Dec 19, 2024
47db077
Add test
owlxiao Dec 19, 2024
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15 changes: 15 additions & 0 deletions lib/Conversion/ImportVerilog/Statements.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -662,6 +662,21 @@ struct StmtVisitor {
return false;
}

/// Handle procedural assign statements.
LogicalResult visit(const slang::ast::ProceduralAssignStatement &stmt) {
if (stmt.isForce) {
auto loc = context.convertLocation(stmt.sourceRange);
mlir::emitError(loc, "force assignments not supported.");
return mlir::failure();
}

auto value = context.convertRvalueExpression(stmt.assignment);
if (!value)
return mlir::failure();

return mlir::success();
}

/// Create the optional diagnostic message print for finish-like ops.
void createFinishMessage(const slang::ast::Expression *verbosityExpr) {
unsigned verbosity = 1;
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4 changes: 4 additions & 0 deletions test/Conversion/ImportVerilog/basic.sv
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Expand Up @@ -595,6 +595,10 @@ module Statements;
// CHECK: [[TMP1:%.+]] = moore.read %y
// CHECK: moore.nonblocking_assign %x, [[TMP1]] : i1
x <= y;

// CHECK: [[TMP1:%.+]] = moore.read %y
// CHECK: moore.blocking_assign %x, [[TMP1]] : i1
assign x = y;
Comment on lines +598 to +601
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Based on SystemVerilog IEEE Std 1800-2017 § 10.6 "Procedural continuous assignments", the assign x = y; should be treated as a continuous assignment.
image

Therefore, I think maybe we should translate this into moore.assign, rather than moore.blocking_assign. WDYH 🤔? @fabianschuiki

end
endmodule

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