Merge branch 'llvm:main' into add-case-inside

llvm · Jan 15, 2025 · dcf122c · dcf122c
2 parents 83e9720 + d53c2d0
commit dcf122c
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diff --git a/.github/workflows/unifiedBuildTestAndInstall.yml b/.github/workflows/unifiedBuildTestAndInstall.yml
@@ -8,10 +8,14 @@ on:
         required: true
         type: choice
         options:
+          - ubuntu-24.04
           - ubuntu-22.04
           - ubuntu-20.04
+          - macos-15-large
+          - macos-15
+          - macos-14-large
+          - macos-14
           - macos-13
-          - macos-12
           - windows-2022
           - windows-2019
       cmake_build_type:

diff --git a/.github/workflows/uploadReleaseArtifacts.yml b/.github/workflows/uploadReleaseArtifacts.yml
@@ -101,7 +101,7 @@ jobs:
         if: github.event_name == 'release' || ( github.event_name == 'workflow_dispatch' && inputs.os == 'macos' )
         env:
           os: macos
-          runner: macos-12
+          runner: macos-13
           arch: x64
           tar: gtar czf
           archive: tar.gz

diff --git a/.github/workflows/uploadWheels.yml b/.github/workflows/uploadWheels.yml
@@ -26,9 +26,9 @@ jobs:
             cibw_build: cp38-manylinux_x86_64
           - os: ubuntu-20.04
             cibw_build: cp310-manylinux_x86_64
-          - os: macos-12
+          - os: macos-13
             cibw_build: cp38-macosx_x86_64
-          - os: macos-12
+          - os: macos-13
             cibw_build: cp310-macosx_x86_64
 
     steps:

diff --git a/docs/Dialects/FIRRTL/FIRRTLAnnotations.md b/docs/Dialects/FIRRTL/FIRRTLAnnotations.md
@@ -345,6 +345,34 @@ The options are:
 }
 ```
 
+### BodyTypeLoweringAnnotation
+
+| Property            | Type   | Description                                          |
+| ------------------- | ------ | ---------------------------------------------------- |
+| class               | string | `circt.BodyTypeLoweringAnnotation`                   |
+| convention          | string | See `Convention` annotation                          |
+| target              | string | See `Convention` annotation                          |
+| includeHierarchy    | bool   | Apply the convention to all modules in the hierarchy |
+
+Specify the type lowering option for module internal signals.
+This is similar to the `Convention` annotation, but for internal signals
+rather than module ports. Refer to the `Convention` annotation for each
+property description.
+
+When `includeHierarchy` is `false`, it indicates the convention is applied only to
+the specified module. If `includeHierarchy` is `true`, the convention is applied to
+all modules in the hierarchy. If there are multiple annotation instances that specify
+conventions, the `scalarized` convention takes precedence over the `internal` convention.
+
+```json
+{
+  "class": "circt.BodyTypeLoweringAnnotation",
+  "convention": "scalarized",
+  "target": "~Foo|Bar",
+  "includeHierarchy": true
+}
+```
+
 ### ElaborationArtefactsDirectory
 
 | Property   | Type   | Description                                              |
@@ -704,33 +732,6 @@ Example:
 }
 ```
 
-### NestedPrefixModulesAnnotation
-
-| Property   | Type   | Description                                              |
-| ---------- | ------ | -------------                                            |
-| class      | string | `sifive.enterprise.firrtl.NestedPrefixModulesAnnotation` |
-| prefix     | string | Prefix to use                                            |
-| inclusive  | bool   | Whether this prefix is inclusive of the target           |
-
-This annotations prefixes all module names under the target with the required
-prefix.  If `inclusive` is true, it includes the target module in the renaming.
-If `inclusive` is false, it will only rename modules instantiated underneath
-the target module.  If a module is required to have two different prefixes, it
-will be cloned.
-
-This annotation is also applied to any interfaces or modules generated by the
-Grand Central Views/Interfaces pass.  This annotation is applied _before_
-`PrefixInterfacesAnnotation`.
-
-Example:
-```json
-{
-  "class": "sifive.enterprise.firrtl.NestedPrefixModulesAnnotation",
-  "prefix": "MyPrefix_",
-  "inclusive": true
-}
-```
-
 ### RetimeModuleAnnotation
 
 | Property   | Type   | Description                                              |
@@ -889,9 +890,9 @@ Example:
 | group       | string | Name of an optional wrapper module under which to group extracted instances |
 
 This annotation causes the `ExtractInstances` pass to move instances of
-extmodules with defname `EICG_wrapper` upwards in the hierarchy, either out of
-the DUT if `group` is omitted or empty, or into a submodule of the DUT with the
-name given in `group`. The wiring prefix is hard-coded to `clock_gate`.
+extmodules whose defnames end in `EICG_wrapper` upwards in the hierarchy, either
+out of the DUT if `group` is omitted or empty, or into a submodule of the DUT
+with the name given in `group`. The wiring prefix is hard-coded to `clock_gate`.
 
 Applies to the circuit.
 
@@ -1174,29 +1175,6 @@ Example:
 }
 ```
 
-#### PrefixInterfacesAnnotation
-
-| Property | Type   | Description                                               |
-|----------|--------|-----------------------------------------------------------|
-| class    | string | sifive.enterprise.grandcentral.PrefixInterfacesAnnotation |
-| prefix   | string | A prefix to apply to all interface names                  |
-
-This annotation can be used to set a global prefix for all interfaces generated
-by Grand Central, including nested interfaces.  The prefix will be applied
-_after_ any prefixes set by `NestedPrefixModulesAnnotation`.
-
-This annotation may only exist zero or one times.  This differs from the SFC
-implementation which will choose the first instance of this annotation.
-
-Example:
-
-``` json
-{
-  "class": "sifive.enterprise.grandcentral.PrefixInterfacesAnnotation",
-  "prefix": "PREFIX_"
-}
-```
-
 #### GrandCentralHierarchyFileAnnotation
 
 | Property | Type   | Description                                                              |

diff --git a/docs/Dialects/RTG.md b/docs/Dialects/RTG.md
@@ -268,8 +268,12 @@ companion dialect to define any backends.
 
 ## Operations
 
-[include "Dialects/RTGOps.md]
+[include "Dialects/RTGOps.md"]
 
 ## Types
 
-[include "Dialects/RTGTypes.md]
+[include "Dialects/RTGTypes.md"]
+
+## Passes
+
+[include "RTGPasses.md"]
diff --git a/docs/ToolsWorkarounds.md b/docs/ToolsWorkarounds.md
@@ -133,3 +133,28 @@ cause the bug to manifest (since they are version dependent), thus there isn't
 a universal fix that can be applied in the generated verilog.
 
 https://github.com/llvm/circt/commit/e9f443be475e0ef796c0c6af1ce09d6e783fcd5a
+
+# Clock Gates and Enables Not Recognized For Registers
+
+Clock gates in some rtl-based power estimation tools are unable to recognize
+clock gates and enables if they are not generated as if statements in always
+blocks.  This is a very narrow pattern match with significant implications for
+the tools lint results and quality of analysis results.
+
+## Example
+```
+  %count = seq.firreg %2 clock %clock sym @count : i2
+  %1 = comb.mux %cond, %value, %count : i2		  %1 = comb.mux bin %cond, %value, %count : i2
+  %2 = comb.mux %reset, %c0_i2, %1 : i2		  %2 = comb.mux bin %reset, %c0_i2, %1 : i2
+```
+
+The mux on `cond` must become an `if` in the output since it forms a self-loop
+on the register `count`.
+
+## Workaround
+
+Effort at several points in lowering make effort to find self-loops through 
+register read and write ports and muxes.  These are generated as `if` statements 
+in the always block that updates the register.
+
+https://github.com/llvm/circt/pull/3815