[ImportVerilog] Support for Procedural assign statements #28470
Triggered via pull request
December 19, 2024 09:31
owlxiao
Status
Success
Total duration
13m 30s
Artifacts
–
buildAndTest.yml
on: pull_request
Sanity Check
33s
Matrix: Build and Test
Annotations
1 warning
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Sanity Check
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636
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