SB_HFOSC support.

src/main/scala/ee/hrzn/chryse/platform/cxxrtl/CxxrtlZigPlatform.scala

@@ -54,6 +54,7 @@ abstract class CxxrtlZigPlatform(id: String) extends CxxrtlPlatform(id) {
       Seq(
         "zig",
         "build",
+        s"-Dclock_hz=$clockHz",
         s"-Dyosys_data_dir=$yosysDatDir",
         s"-Dcxxrtl_o_paths=${ccOutPaths.map(p => s"../$p").mkString(",")}",
       )

src/main/scala/ee/hrzn/chryse/platform/ice40/Ice40Top.scala

@@ -28,6 +28,7 @@ import ee.hrzn.chryse.platform.PlatformBoard
 import ee.hrzn.chryse.platform.PlatformBoardResources
 import ee.hrzn.chryse.platform.ice40.inst.PinType
 import ee.hrzn.chryse.platform.ice40.inst.SB_GB_IO
+import ee.hrzn.chryse.platform.ice40.inst.SB_HFOSC
 import ee.hrzn.chryse.platform.ice40.inst.SB_IO
 import ee.hrzn.chryse.platform.resource.PinInt
 import ee.hrzn.chryse.platform.resource.ResourceData
@@ -96,13 +97,25 @@ class Ice40Top[Top <: Module](
     }
   }
 
-  private val clki = Wire(Clock())
+  private val default_clock = Wire(Clock())
 
-  private val clk_gb = Module(new SB_GB_IO)
-  clk_gb.PACKAGE_PIN := clki
-  private val clk = clk_gb.GLOBAL_BUFFER_OUTPUT
+  private val clk        = Wire(Clock())
+  private var timerLimit = (15 * platform.clockHz / 1_000_000).toInt
+
+  // XXX
+  if (platform.asInstanceOf[IceBreakerPlatform].useHfosc.isDefined) {
+    val hfosc = Module(new SB_HFOSC(div = 1))
+    hfosc.CLKHFEN := true.B
+    hfosc.CLKHFPU := true.B
+    clk           := hfosc.CLKHF
+
+    timerLimit = (100 * platform.clockHz / 1_000_000).toInt
+  } else {
+    val clk_gb = Module(new SB_GB_IO)
+    clk_gb.PACKAGE_PIN := default_clock
+    clk                := clk_gb.GLOBAL_BUFFER_OUTPUT
+  }
 
-  private val timerLimit = (15 * platform.clockHz / 1_000_000).toInt
   private val resetTimerReg =
     withClock(clk)(Reg(UInt(unsignedBitLength(timerLimit).W)))
   private val reset = Wire(Bool())
@@ -129,10 +142,8 @@ class Ice40Top[Top <: Module](
   if (top.desiredName == desiredName)
     throw new IllegalArgumentException(s"user top is called $desiredName")
 
-  // TODO (iCE40): allow clock source override.
-
   private val connectedResources =
-    connectResources(platform, Some(clki))
+    connectResources(platform, Some(default_clock))
 
   val pcf = Pcf(
     connectedResources

src/main/scala/ee/hrzn/chryse/platform/ice40/IceBreakerPlatform.scala

@@ -32,10 +32,18 @@ import ee.hrzn.chryse.platform.resource.Uart
 case class IceBreakerPlatform(
     ubtnReset: Boolean = false,
     inferSpram: Boolean = false,
+    useHfosc: Option[Int] = None,
 ) extends PlatformBoard[IceBreakerPlatformResources]
     with Ice40Platform {
-  val id      = "icebreaker"
-  val clockHz = 12_000_000
+  val id = "icebreaker"
+  val clockHz = useHfosc match {
+    case None      => 12_000_000
+    case Some(0)   => 48_000_000
+    case Some(1)   => 24_000_000
+    case Some(2)   => 12_000_000
+    case Some(3)   => 6_000_000
+    case Some(div) => throw new IllegalArgumentException(s"bad HFOSC div $div")
+  }
 
   override val ice40Args    = if (inferSpram) Seq("-spram") else Seq()
   override val ice40Variant = UP5K

src/main/scala/ee/hrzn/chryse/platform/ice40/inst/SB_HFOSC.scala

@@ -0,0 +1,31 @@
+/* Copyright © 2024 Asherah Connor.
+ *
+ * This file is part of Chryse.
+ *
+ * Chryse is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU Lesser General Public License as published by the Free
+ * Software Foundation, either version 3 of the License, or (at your option) any
+ * later version.
+ *
+ * Chryse is distributed in the hope that it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+ * A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with Chryse. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+package ee.hrzn.chryse.platform.ice40.inst
+
+import chisel3._
+import chisel3.experimental.ExtModule
+
+class SB_HFOSC(div: Int)
+    extends ExtModule(
+      Map("CLKHF_DIV" -> f"0b${div.toBinaryString.toInt}%02d"), // kill me
+    ) {
+  val CLKHFEN = IO(Input(Bool()))
+  val CLKHFPU = IO(Input(Bool()))
+  val CLKHF   = IO(Output(Clock()))
+}