[riscv] Init support for RISCV vector extension

jfalcou · Aug 14, 2024 · 492c84d · 492c84d
1 parent c1f74e3
commit 492c84d
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diff --git a/cmake/toolchain/clang.rvv128.cmake b/cmake/toolchain/clang.rvv128.cmake
@@ -0,0 +1,19 @@
+##==================================================================================================
+##  EVE - Expressive Vector Engine
+##  Copyright : EVE Project Contributors
+##  SPDX-License-Identifier: BSL-1.0
+##==================================================================================================
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_PROCESSOR riscv64)
+
+set(CMAKE_C_COMPILER   	clang  )
+set(CMAKE_CXX_COMPILER  clang++  )
+
+
+if(NOT DEFINED ENV{RISCV_GCC})
+  message(FATAL_ERROR "expected to have RISCV_GCC in environment")
+endif()
+
+set(CMAKE_CXX_FLAGS "-O3 -march=rv64gcv -std=c++20 -mrvv-vector-bits=128 --sysroot=$ENV{RISCV_GCC}/sysroot --gcc-toolchain=$ENV{RISCV_GCC} --static --target=riscv64-unknown-linux-gnu ${EVE_OPTIONS}" )
+
+set(CMAKE_CROSSCOMPILING_CMD ${PROJECT_SOURCE_DIR}/cmake/toolchain/run_rvv128.sh )
diff --git a/cmake/toolchain/run_rvv128.sh b/cmake/toolchain/run_rvv128.sh
@@ -0,0 +1,8 @@
+##==================================================================================================
+##  EVE - Expressive Vector Engine
+##  Copyright : EVE Project Contributors
+##  SPDX-License-Identifier: BSL-1.0
+##==================================================================================================
+#!/bin/sh
+
+qemu-riscv64 --cpu rv64,v=true,vlen=128 $@
diff --git a/include/eve/arch/abi_of.hpp b/include/eve/arch/abi_of.hpp
@@ -65,6 +65,7 @@ namespace eve
             else                                   return emulated_{};
           }
         }
+        else if constexpr( spy::simd_instruction_set == spy::rvv_ ) { return riscv_rvv_dyn_ {}; }
         else
         {
           return emulated_{};

diff --git a/include/eve/arch/as_register.hpp b/include/eve/arch/as_register.hpp
@@ -10,9 +10,10 @@
 #include <eve/arch/cpu/as_register.hpp>
 
 #if !defined(EVE_NO_SIMD)
-#include <eve/arch/x86/as_register.hpp>
-#include <eve/arch/ppc/as_register.hpp>
-#include <eve/arch/arm/sve/as_register.hpp>
-#include <eve/arch/arm/neon/as_register.hpp>
+#  include <eve/arch/arm/neon/as_register.hpp>
+#  include <eve/arch/arm/sve/as_register.hpp>
+#  include <eve/arch/ppc/as_register.hpp>
+#  include <eve/arch/riscv/as_register.hpp>
+#  include <eve/arch/x86/as_register.hpp>
 #endif
-Original file line number
+Diff line change
@@ Expand Up / @@ -65,6 +65,7 @@ namespace eve @@
                 else                                   return emulated_{};
               }
             }
+            else if constexpr( spy::simd_instruction_set == spy::rvv_ ) { return riscv_rvv_dyn_ {}; }
             else
             {
               return emulated_{};
@@ Expand Down @@