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handle hready in ahb writing
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M0stafaRady committed Oct 14, 2024
1 parent 6b740bd commit 2e42a42
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Showing 2 changed files with 12 additions and 7 deletions.
7 changes: 6 additions & 1 deletion bus_env/bus_agent/bus_ahb_driver.py
Original file line number Diff line number Diff line change
Expand Up @@ -79,13 +79,18 @@ async def data_phase(self, tr):
uvm_info(
self.tag,
f"tr at the start of data phase {tr.convert2string()} sequence id {tr.id}",
UVM_HIGH,
UVM_LOW,
)
if tr.kind == bus_item.WRITE:
self.vif.HWDATA.value = tr.data
await NextTimeStep()
if self.vif.HREADYOUT.value == 0:
self.vif.HREADY.value = 0b0
await self.drive_delay()
while self.vif.HREADYOUT.value == 0:
self.vif.HREADY.value = 0b0
await self.drive_delay()
self.vif.HREADY.value = 0b1
else:
# for reading just wait until the data is ready
if self.vif.HREADYOUT.value == 0:
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12 changes: 6 additions & 6 deletions bus_env/bus_regs.py
Original file line number Diff line number Diff line change
Expand Up @@ -233,24 +233,24 @@ def write_reg_value(self, reg, value, mask=0xFFFFFFFF, force_write=False):
)
cocotb.scheduler.add(self.update_delayed_reg(address))

def __read_reg_value(self, reg, delayed=False):
def __read_reg_value(self, reg, delayed=False,mask = 0xFFFF):
if type(reg) is int:
address = reg
elif type(reg) is str:
address = self.reg_name_to_address[reg]
else:
uvm_error(self.tag, f"Invalid reg type: {type(reg)} for read")
address = address & 0xFFFF
address = address & mask
if delayed:
return self.regs[address]["delayed_val"]
else:
return self.regs[address]["val"]

def read_reg_value(self, reg):
return self.__read_reg_value(reg)
def read_reg_value(self, reg, delayed=False,mask = 0xFFFF):
return self.__read_reg_value(reg, mask=mask, delayed=delayed)

def read_reg_value_delayed(self, reg):
return self.__read_reg_value(reg, delayed=True)
def read_reg_value_delayed(self, reg, mask=0xFFFF):
return self.__read_reg_value(reg, delayed=True, mask=mask)

# Function to replace parameter values in the data
def replace_parameters(self, data, parameter_values):
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