update the design name

efabless · Oct 10, 2024 · 239e6df · 239e6df
1 parent 1bb9131
commit 239e6df
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
@@ -13,7 +13,7 @@ BUS_TYPE ?= AHB
 GL_MACROS += -DFUNCTIONAL 
 # GL_MACROS += "$(RTL_MACROS) -DFUNCTIONAL -DUNIT_DELAY=##1"
 ## netlist Gen 
-DESIGN_NAME = MS_QSPI_XIP_CACHE_ahbl
+DESIGN_NAME = EF_QSPI_XIP_CTRL_ahbl
 PRE_SYS_FILES = $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
 PDK_DIR = $(HOME)/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/
 PDK_FILES = $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v # get this from openlane logs in the future