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  1. OpenCGRA OpenCGRA Public

    Forked from pnnl/OpenCGRA

    OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

    Verilog

  2. uSystolic-Sim uSystolic-Sim Public

    Forked from diwu1990/uSystolic-Sim

    A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

    C++

  3. ThunderGP ThunderGP Public

    Forked from Xtra-Computing/ThunderGP

    HLS-based Graph Processing Framework on FPGAs

    C++

  4. HitGraph HitGraph Public

    Forked from pgroupATusc/HitGraph

    Source code for "HitGraph: High-throughput Graph Processing"

    Verilog

  5. ReGraph ReGraph Public

    Forked from Xtra-Computing/ReGraph

    Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines

    C++

  6. HitGraph_basic HitGraph_basic Public

    Forked from joshjiejie/HitGraph

    Graph processing acceleration

    Verilog