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Add bool for writing to destination reg to RVFI output #61

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Add bool for writing to destination reg to RVFI output #61

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2 changes: 1 addition & 1 deletion src/cheri_insts.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -707,7 +707,7 @@ function clause execute (CClear(q, m)) = {
if q_u == 0 & i == 0 then
DDC = null_cap
else
C(8 * q_u + i) = null_cap;
wC (false, 8 * q_u + i, null_cap);
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This is the bit that will show in the ISA doc, and the no-context false may be confusing. I wonder if there's a clearer way, for example wrapping wc(false, ....) in a function. Not sure what to call that function though, since RVFI isn't really visible from the instruction-level description.

RETIRE_SUCCESS
}

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14 changes: 9 additions & 5 deletions src/cheri_regs.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -103,8 +103,8 @@ function rC r = {
}

/* writes a register with a capability value */
val wC : forall 'n, 0 <= 'n < 32. (regno('n), regtype) -> unit effect {wreg, escape}
function wC (r, v) = {
val wC : forall 'n, 0 <= 'n < 32. (bool, regno('n), regtype) -> unit effect {wreg, escape}
function wC (b, r, v) = {
match r {
0 => (),
1 => x1 = v,
Expand Down Expand Up @@ -141,17 +141,21 @@ function wC (r, v) = {
_ => internal_error(__FILE__, __LINE__, "Invalid capability register")
};
if (r != 0) then {
rvfi_wX(r, v.address);
if b then
rvfi_wX(r, v.address);
if get_config_print_reg() then
print_reg("x" ^ dec_str(r) ^ " <- " ^ RegStr(v));
}
}

function rC_bits(r: bits(5)) -> regtype = rC(unsigned(r))

function wC_bits(r: bits(5), v: regtype) -> unit = wC(unsigned(r), v)
function wC_bits(r: bits(5), v: regtype) -> unit = wC (true, unsigned(r), v)

overload C = {rC_bits, wC_bits, rC, wC}
val wC_rvfi : forall 'n, 0 <= 'n < 32. (regno('n), regtype) -> unit effect {wreg, escape}
function wC_rvfi (r, v) = wC (true, r, v)

overload C = {rC_bits, wC_bits, rC, wC_rvfi}

val ext_init_regs : unit -> unit effect {wreg}
function ext_init_regs () = {
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