CHERI riscv: optionally trap on PTE_{A,D,CD} clear

These are `#if 0`-ed out, but has proven useful in testing, as our FPGA cores
trap rather than atomically update the PTE.

target/riscv/cpu_helper.c

@@ -362,6 +362,17 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
 extern bool rvfi_debug_output;
 #endif
 
+#ifndef RISCV_PTE_TRAPPY
+/*
+ * The PTW logic below supports trapping on any subset of PTE_A, PTE_D, PTE_CD
+ * being clear during an access that would have them be set.  The RISC-V spec
+ * says that PTE_A and PTE_D always go together, and it's probably most sensible
+ * that PTE_CD implies PTE_A and PTE_D.  So, sensible values for this constant
+ * are 0, (PTE_A | PTE_D), or (PTE_A | PTE_D | PTE_CD).
+ */
+#define RISCV_PTE_TRAPPY 0
+#endif
+
 /* get_physical_address - get the physical address for this virtual address
  *
  * Do a page table walk to obtain the physical address corresponding to a
@@ -614,10 +625,26 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) {
             /* Fetch access check failed */
             return TRANSLATE_FAIL;
+#if RISCV_PTE_TRAPPY & PTE_D
+        } else if ((access_type == MMU_DATA_STORE ||
+                    access_type == MMU_DATA_CAP_STORE) && !(pte & PTE_D)) {
+            /* PTE not marked as dirty */
+            return TRANSLATE_FAIL;
+#endif
 #if defined(TARGET_CHERI) && !defined(TARGET_RISCV32)
         } else if (access_type == MMU_DATA_CAP_STORE && !(pte & PTE_CW)) {
             /* CW inhibited */
             return TRANSLATE_CHERI_FAIL;
+#if RISCV_PTE_TRAPPY & PTE_CD
+        } else if (access_type == MMU_DATA_CAP_STORE && !(pte & PTE_CD)) {
+            /* CD clear; force the software trap handler to get involved */
+            return TRANSLATE_CHERI_FAIL;
+#endif
+#endif
+#if RISCV_PTE_TRAPPY & PTE_A
+        } else if (!(pte & PTE_A)) {
+            /* PTE not marked as accessed */
+            return TRANSLATE_FAIL;
 #endif
         } else {
             /* if necessary, set accessed and dirty bits. */