CHERI MIPS: don't clobber CLG bits in MMU fault

When raising a MMU exception, we were zeroing out the CLG bits from CP0 EntryHi, which was, understandably, making software sad. Fixes 7c74ddc and f0feea1
CTSRD-CHERI · Apr 26, 2021 · cbd9b41 · cbd9b41
1 parent 35c3753
commit cbd9b41
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Showing 4 changed files with 11 additions and 10 deletions.
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
@@ -1281,11 +1281,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
     mask &= env->SEGMask;
 #endif
 
-#if defined(TARGET_CHERI)
-    mask |= (1UL << CP0EnHi_CLGU)
-            | (1UL << CP0EnHi_CLGS)
-            | (1UL << CP0EnHi_CLGK);
-#endif
+    mask |= CP0EnHi_CLG_MASK;
 
     old = env->CP0_EntryHi;
     val = (arg1 & mask) | (old & ~mask);

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
@@ -820,6 +820,10 @@ struct CPUMIPSState {
 #define CP0EnHi_CLGK 61
 #define CP0EnHi_CLGS 60
 #define CP0EnHi_CLGU 59
+#define CP0EnHi_CLG_MASK \
+    ((1ULL << CP0EnHi_CLGK) | (1ULL << CP0EnHi_CLGS) | (1UL << CP0EnHi_CLGU))
+#else
+#define CP0EnHi_CLG_MASK 0
 #endif
     target_ulong CP0_EntryHi_ASID_mask;
 /*

diff --git a/target/mips/helper.c b/target/mips/helper.c
@@ -614,10 +614,11 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
                        ((address >> 9) & 0x007ffff0);
     env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
+                       (env->CP0_EntryHi & CP0EnHi_CLG_MASK) |
                        (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
                        (address & (TARGET_PAGE_MASK << 1));
 #if defined(TARGET_MIPS64)
-    env->CP0_EntryHi &= env->SEGMask;
+    env->CP0_EntryHi &= env->SEGMask | CP0EnHi_CLG_MASK;
     env->CP0_XContext =
         (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
         (extract64(address, 62, 2) << (env->SEGBITS - 9)) |     /* R       */
@@ -956,7 +957,8 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw,
     }
     pw_pagemask = m >> 12;
     update_pagemask(env, pw_pagemask << 13, &pw_pagemask);
-    pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
+    pw_entryhi = (address & ~0x1fff) |
+                 (env->CP0_EntryHi & (0xFF | CP0EnHi_CLG_MASK));
     {
         target_ulong tmp_entryhi = env->CP0_EntryHi;
         int32_t tmp_pagemask = env->CP0_PageMask;

diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
@@ -959,8 +959,7 @@ void r4k_helper_tlbr(CPUMIPSState *env)
     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
 
 #ifdef CPU_CHERI
-	uint64_t save_clg = env->CP0_EntryHi &
-		((1 << CP0EnHi_CLGU) | (1 << CP0EnHi_CLGS) | (1 << CP0EnHi_CLGK));
+    uint64_t save_clg = env->CP0_EntryHi & CP0EnHi_CLG_MASK;
 #endif
 
     if (tlb->EHINV) {
@@ -997,7 +996,7 @@ void r4k_helper_tlbr(CPUMIPSState *env)
     }
 
 #ifdef CPU_CHERI
-	env->CP0_EntryHi |= save_clg;
+    env->CP0_EntryHi |= save_clg;
 #endif
 }