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I have posted the same question on the mailing list, but somehow I cannot reply to my conversation anymore (all of my messages got automatically deleted). So I have to post this question again here and also reclarify my problem.
Google mailing list: https://groups.google.com/g/chipyard/c/r6-R74akUvw
In general, I want to implement my DUT in FPGA and transmit the executable binary for DUT using a host CPU via UART ports. Based on the suggestion in https://groups.google.com/g/chipyard/c/7w4xkMz_E14/m/bQaakOAWAAAJ, I have tried the chipyard config TetheredChipLikeRocketConfig and as mentioned by Joonho in my mailing list, the attribute WithUartSerialTl provides the FPGA-synthesizable hardware modules for converting UART to serialTL, so the FPGA implementation with UART port for binary receiving is complete.
However, the problem on the host side implementation still exists. The current driver implementation in the TetheredChipLikeRocketConfig is SimTSI + several hardware modules for TSI-to-UART conversion, where these hardware modules cannot be implemented on a host CPU.
Config setting:
Generated verilog code:
Therefore, I wonder if here exists a software driver for this condition. Based on my search, the 'uart_tsi' from testchipip github seems to match my need: https://github.com/ucb-bar/testchipip/tree/master
I have successfully generated the executable for 'uart_tsi', but I haven't found any documents or guidance on how to apply this executable on the host CPU and how can it interact with our binary for DUT. Is there any suggestions on this condition?
Background Work
Feature Description
I have posted the same question on the mailing list, but somehow I cannot reply to my conversation anymore (all of my messages got automatically deleted). So I have to post this question again here and also reclarify my problem.
Google mailing list: https://groups.google.com/g/chipyard/c/r6-R74akUvw
In general, I want to implement my DUT in FPGA and transmit the executable binary for DUT using a host CPU via UART ports. Based on the suggestion in https://groups.google.com/g/chipyard/c/7w4xkMz_E14/m/bQaakOAWAAAJ, I have tried the chipyard config TetheredChipLikeRocketConfig and as mentioned by Joonho in my mailing list, the attribute WithUartSerialTl provides the FPGA-synthesizable hardware modules for converting UART to serialTL, so the FPGA implementation with UART port for binary receiving is complete.
However, the problem on the host side implementation still exists. The current driver implementation in the TetheredChipLikeRocketConfig is SimTSI + several hardware modules for TSI-to-UART conversion, where these hardware modules cannot be implemented on a host CPU.
Config setting:
Generated verilog code:
Therefore, I wonder if here exists a software driver for this condition. Based on my search, the 'uart_tsi' from testchipip github seems to match my need:
https://github.com/ucb-bar/testchipip/tree/master
I have successfully generated the executable for 'uart_tsi', but I haven't found any documents or guidance on how to apply this executable on the host CPU and how can it interact with our binary for DUT. Is there any suggestions on this condition?
Motivating Example
Want to have some guidance on implementing the fesvr in a host CPU and transmitting the executable binary via UART to the FPGA DUT. In general, similar to the testing structure in 8.2.3.2 here:
https://chipyard.readthedocs.io/en/latest/Advanced-Concepts/Chip-Communication.html
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