diff --git a/lib/Conversion/ImportVerilog/Statements.cpp b/lib/Conversion/ImportVerilog/Statements.cpp
index fe1bc80f5d2c..f2069f9bb8eb 100644
--- a/lib/Conversion/ImportVerilog/Statements.cpp
+++ b/lib/Conversion/ImportVerilog/Statements.cpp
@@ -208,8 +208,32 @@ struct StmtVisitor {
           cond = builder.create<moore::CaseZEqOp>(itemLoc, caseExpr, value);
           break;
         case CaseStatementCondition::Inside:
-          mlir::emitError(loc, "unsupported set membership case statement");
-          return failure();
+          std::vector<Value> values;
+          values.reserve(item.expressions.size());
+          for (const auto *expr : item.expressions) {
+              auto value = context.convertRvalueExpression(*expr);
+              if (!value)
+                  return failure();
+              values.push_back(value);
+          }
+
+          if (values.empty()) {
+              mlir::emitError(loc, "empty set in inside case statement");
+              return failure();
+          }
+
+          if (values.size() == 1) {
+              cond = builder.create<moore::CaseEqOp>(
+                  loc, caseExpr, values.front());
+          } else {
+              cond = builder.create<moore::CaseEqOp>(loc, caseExpr, values[0]);
+              for (size_t i = 1; i < values.size(); ++i) {
+                  auto nextCond = builder.create<moore::CaseEqOp>(
+                      loc, caseExpr, values[i]);
+                  cond = builder.create<mlir::arith::OrIOp>(loc, builder.getI1Type(), cond,
+                                                    nextCond);
+              }
+          }
         }
         cond = builder.create<moore::ConversionOp>(itemLoc, builder.getI1Type(),
                                                    cond);