Comparison to Verilog

A few quick examples of Verilog code, and then the equivalent in Chisel.

example of boolean logic, with named wires feeding values in and a named wire as output:

example of a wire that feeds a value into a register, where register is triggered at every rising clock edge:

example of a mux, with named wires feeding in, and a named wire accepting output:

For reference, here is an incomplete, in-development table of (close to) one-to-one resemblance between Verilog and Chisel. Please do not spend to much time here, especially not in the first pass, rather use this table as a reference as you go along the Learning Journey.

Verilog	Example in Verilog	Chisel	Example in Chisel
create a module	module full_adder (a, b, y); ... endmodule	Scala class definition	class FullAdder(...) extends Module { ... }
input/output ports	input a, b; output z;	create interfaces within a Bundle	val io = IO(new Bundle { val a = Input(...) val b = Input(...) val y = Output(...) })
specify synchronous logic	always @ (posedge clk);	operation performed when the condition is true	when (condition) { expression }

Next Steps

Once you've scrolled through these, not more than a couple of minutes, please proceed to the next step of the Learning Journey.