CPU Current limit unlock #464

gundami · 2023-11-13T05:51:30Z

gundami
Nov 13, 2023

I'm using corefreq to overclock my cpu, but i can't find any configuaration file. It's too troublesome to reconfigure every time I start up.
ps: corefreq lacks the ability to adjust the upper current limit, i'm using throttled to implement this function。

cyring · 2023-11-13T06:39:04Z

cyring
Nov 13, 2023
Maintainer

I'm using corefreq to overclock my cpu, but i can't find any configuaration file. It's too troublesome to reconfigure every time I start up.

CoreFreq is using kernel module parameters.
Those are usually stored in the common Linux path of /etc/modprobe.conf
You can also set parameters in the kernel boot command line.

All possible parameters are managed using standard commands.
To list them:

modinfo /yourpathto/corefreqk.ko

ps: corefreq lacks the ability to adjust the upper current limit, i'm using throttled to implement this function。

Do you know the Register for this current limit ?
At best, I'm providing the PL, Power Limiter.
You didn't show me your processor using corefreq-cli -s
Does it have PL ?

0 replies

gundami · 2023-11-14T02:34:12Z

gundami
Nov 14, 2023
Author

You can also set parameters in the kernel boot command line.

Thanks, i get it.

Do you know the Register for this current limit ?

I'm not sure, i find some code in the Throttled repo:

def set_icc_max(config):
    for plane in CURRENT_PLANES:
        try:
            write_current_amp = config.getfloat(
                'ICCMAX.{:s}'.format(power['source']), plane, fallback=config.getfloat('ICCMAX', plane, fallback=-1.0)
            )
            if write_current_amp > 0:
                write_value = calc_icc_max_msr(plane, write_current_amp)
                writemsr('MSR_OC_MAILBOX', write_value)
                if args.debug:
                    write_value &= 0x3FF
                    read_value = get_icc_max(plane)[plane]
                    read_current_A = calc_icc_max_amp(read_value)
                    match = OK if write_value == read_value else ERR
                    log(
                        '[D] IccMax plane {:s} - write {:.2f} A ({:#x}) - read {:.2f} A ({:#x}) - match {}'.format(
                            plane, write_current_amp, write_value, read_current_A, read_value, match
                        )
                    )
        except (configparser.NoSectionError, configparser.NoOptionError):
            pass

On my cpu, if i don't increase the current limit, the cpu power will be limited at 100w, though i set PL to 180w.
And this is my processor info, my cpu is Q1HY, the engineering example of i9 13900H.
In my bios i set PL to 200w. The PL below is 500w, set by throttled, just in case.

Processor                                                [Genuine Intel(R) 0000]
|- Architecture                                                  [Raptor Lake/P]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x0000410e]
|- Signature                                                           [  06_BA]
|- Stepping                                                            [      2]
|- Online CPU                                                          [ 20/ 20]
|- Base Clock                                                          [100.426]
|- Frequency            (MHz)                      Ratio                        
                 Min    401.70                    <   4 >                       
                 Max   2611.07                    <  26 >                       
|- Factory                                                             [100.000]
                       2600                       [  26 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT   6929.39                    <  69 >                       
   |- HWP                                                                       
                 Min   6929.39                    <  69 >                       
                 Max   6929.39                    <  69 >                       
                 TGT      AUTO                    <   0 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   5423.00                    <  54 >                       
                  2C   5423.00                    <  54 >                       
                  3C   5423.00                    <  54 >                       
                  4C   5423.00                    <  54 >                       
                  5C   5222.15                    <  52 >                       
                  6C   5222.15                    <  52 >                       
                  7C   5222.15                    <  52 >                       
                  8C   5222.15                    <  52 >                       
|- Hybrid                                                              [ UNLOCK]
                  1C   4017.10                    <  40 >                       
                  2C   4017.10                    <  40 >                       
                  3C   3816.24                    <  38 >                       
                  4C   3816.24                    <  38 >                       
                  5C   3816.24                    <  38 >                       
                  6C   3816.24                    <  38 >                       
                  7C   3816.24                    <  38 >                       
                  8C   3816.24                    <  38 >                       
|- Uncore                                                              [ UNLOCK]
                 Min    401.71                    <   4 >                       
                 Max   4720.09                    <  47 >                       
|- TDP                                                           Level <  0:3  >
   |- Programmable                                                     [ UNLOCK]
   |- Configuration                                                    [ UNLOCK]
   |- Turbo Activation                                                 [ UNLOCK]
             Nominal   2209.37                    [  22 ]                       
              Level1   1606.81                    [  16 ]                       
              Level2   2611.07                    [  26 ]                       
               Turbo   2108.94                    <  21 >                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AMX-BF16     [N]     AMX-TILE [N]     AMX-INT8 [N]    AMX-FP16 [N] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [Y] AVX-VNN-INT8 [N] AVX-NE-CONV [N] 
|- AVX-IFMA     [N]    CMPccXADD [N]      MOVDIRI [Y]   MOVDIR64B [Y] 
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- ENQCMD       [N]         GFNI [Y]        OSPKE [Y]     WAITPKG [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [Y]      SYSCALL [Y]        RDPID [Y]         SGX [N] 
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast Short REP CMPSB                                         FSRC   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast Short REP STOSB                                         FSRS   [Capable]
|- Fast Zero-length REP MOVSB                                   FZRM   [Missing]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Feedback Interface                                   HFI   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- History Reset                                              HRESET   [Capable]
|- Hybrid part processor                                      HYBRID   [Capable]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- Linear Address Space Separation                              LASS   [Missing]
|- Linear Address Masking                                        LAM   [Missing]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Platform Configuration                                    PCONFIG   [Capable]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Write Data to a Processor Trace Packet                    PTWRITE   [Capable]
|- PREFETCHIT0/1 Instructions                              PREFETCHI   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Missing]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Capable]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Thread Director                                                TD   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Capable]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Missing]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [ Enable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [Capable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [ Enable]
|- Arch - Buffer Overwriting                                MD-CLEAR   [Capable]
|- Arch - No Rogue Data Cache Load                           RDCL_NO   [ Enable]
|- Arch - Enhanced IBRS                                     IBRS_ALL   [ Enable]
|- Arch - Return Stack Buffer Alternate                         RSBA   [Capable]
|- Arch - No Speculative Store Bypass                         SSB_NO   [Capable]
|- Arch - No Microarchitectural Data Sampling                 MDS_NO   [ Enable]
|- Arch - No TSX Asynchronous Abort                           TAA_NO   [ Enable]
|- Arch - No Page Size Change MCE                     PSCHANGE_MC_NO   [ Enable]
|- Arch - STLB QoS                                              STLB   [ Enable]
|- Arch - Functional Safety Island                              FuSa   [ Enable]
|- Arch - RSM in CPL0 only                                       RSM   [ Enable]
|- Arch - Split Locked Access Exception                         SPLA   [ Enable]
|- Arch - Snoop Filter QoS Mask                         SNOOP_FILTER   [ Enable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Data Operand Independent Timing Mode                 DOITM   [Capable]
|- Arch - Not affected by SBDR or SSDP                  SBDR_SSDP_NO   [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator              FBSDP_NO   [ Enable]
|- Arch - No Primary Stale Data Propagator                   PSDP_NO   [ Enable]
|- Arch - Overwrite Fill Buffer values                      FB_CLEAR   [Capable]
|- Arch - Special Register Buffer Data Sampling                SRBDS   [ Unable]
   |- RDRAND and RDSEED mitigation                             RNGDS   [ Unable]
   |- Restricted Transactional Memory                            RTM   [ Unable]
   |- Verify Segment for Writing instruction                    VERW   [ Unable]
|- Arch - Restricted RSB Alternate                             RRSBA   [ Enable]
|- Arch - No Branch Target Injection                          BHI_NO   [Capable]
|- Arch - Legacy xAPIC Disable                             XAPIC_DIS   [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer               PBRSB_NO   [Capable]
|- Arch - IPRED disabled for CPL3                        IPRED_DIS_U   [Capable]
|- Arch - IPRED disabled for CPL0/1/2                    IPRED_DIS_S   [Capable]
|- Arch - RRSBA disabled for CPL3                        RRSBA_DIS_U   [Capable]
|- Arch - RRSBA disabled for CPL0/1/2                    RRSBA_DIS_S   [Capable]
|- Arch - Data Dependent Prefetcher CPL3                  DDPD_U_DIS   [Capable]
|- Arch - BHI disabled for CPL0/1/2                        BHI_DIS_S   [Capable]
|- No MXCSR Configuration Dependent Timing                   MCDT_NO   [ Unable]
Security Features                                                               
|- CPUID Key Locker                                               KL   [Capable]
|- AES Key Locker instructions                                AESKLE   [Missing]
|- AES Wide Key Locker instructions                          WIDE_KL   [Capable]
|- Software Guard SGX1 Extensions                               SGX1   [Missing]
|- Software Guard SGX2 Extensions                               SGX2   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   <OFF>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [ ON]
|- Hyper-Threading                                                   HTT   [ ON]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost Max 3.0                                             TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   < ON>
|- Race To Halt Optimization                                         R2H   < ON>
|- Watchdog Timer                                                    TCO   <OFF>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [ ON]
   |- Version                                                     [         4.0]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  5]
|- Counters:          General                   Fixed                           
|           {  6,  0,  0 } x 48 bits            3 x 48 bits                     
|- Enhanced Halt State                                           C1E       < ON>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       <OFF>
|- C1 UnDemotion                                                 C1U       < ON>
|- C3 UnDemotion                                                 C3U       <OFF>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [ UNLOCK]
   |- Lowest C-State                                           LIMIT   <     C0>
   |- I/O MWAIT Redirection                                  IOMWAIT   <Disable>
   |- Max C-State Inclusion                                    RANGE   <     C8>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x1814]
|- ACPI Processor C-States                                      _CST   [      3]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     0     2     0     1     0     1              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
|- Processor Performance Control                                _PCT   [ Enable]
|- Performance Supported States                                 _PSS   [      0]
|- Performance Present Capabilities                             _PPC   [      3]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0:100 C>
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [ UNLOCK]
   |- Energy Policy                                        Bias Hint   <      7>
   |- Energy Policy                                          HWP EPP   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Capable]
|- Package Thermal Management                                    PTM   [Capable]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [   45 W]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <  500 W>
   |- Time Window                                                TW1   <  2m08s>
   |- Power Limit                                                PL2   <  500 W>
   |- Time Window                                                TW2   <   2 ms>
|- Thermal Design Power                                         Core   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                       Uncore   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                     Platform   < Enable>
   |- Power Limit                                                PL1   <  200 W>
   |- Time Window                                                TW1   <    1 s>
   |- Power Limit                                                PL2   <  200 W>
   |- Time Window                                                TW2   < 976 us>
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Package Thermal Point                                                        
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000061035]
   |- Window                                            second   [  0.000976562]

0 replies

cyring · 2023-11-14T10:39:16Z

cyring
Nov 14, 2023
Maintainer

I'm not sure, i find some code in the Throttled repo:

Do you have any link to the source code of this repo ?

writemsr('MSR_OC_MAILBOX', write_value)

This MSR Register seems interesting: we need its index value and its protocol specification.

0 replies

cyring · 2023-11-14T10:41:08Z

cyring
Nov 14, 2023
Maintainer

Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   <OFF>

Did you disable this prefetcher on purpose or it's a miss reading of CoreFreq ?

0 replies

gundami · 2023-11-14T11:05:17Z

gundami
Nov 14, 2023
Author

I'm not sure, i find some code in the Throttled repo:

Do you have any link to the source code of this repo ?

writemsr('MSR_OC_MAILBOX', write_value)

This MSR Register seems interesting: we need its index value and its protocol specification.

Here is the link: https://github.com/erpalma/throttled/blob/master/throttled.py

Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   <OFF>

Did you disable this prefetcher on purpose or it's a miss reading of CoreFreq ?

I haven't change it, it seems been set off by default?

0 replies

cyring · 2023-11-14T15:18:07Z

cyring
Nov 14, 2023
Maintainer

Here is the link: https://github.com/erpalma/throttled/blob/master/throttled.py

I have a compatible Nehalem Xeon W3690 but unfortunately reading Mailbox MSR is not supported.

# rdmsr -a 0x150
rdmsr: CPU 0 cannot read MSR 0x00000150

Whereas all the other MSR (listed in throttled) are already implemented in CoreFreq

0 replies

cyring · 2023-11-14T15:32:29Z

cyring
Nov 14, 2023
Maintainer

If supported, you can also try TDC, parameter Custom_TDC_Offset

Here after Enabling the feature, I'm adding 3 amps

You can check support of the MSR_TURBO_POWER_CURRENT_LIMIT to alter amps.
Try the following MSR read like my W3690 :

rdmsr -a 0x000001ac

You may also have a chance with Thermal Offset which is added or subtracted to the TjMax

It's an architectural register, try to test directly MSR_IA32_TEMPERATURE_TARGET:

rdmsr -a 0x000001a2

0 replies

gundami · 2023-11-15T03:21:58Z

gundami
Nov 15, 2023
Author

If supported, you can also try TDC, parameter Custom_TDC_Offset

Here after Enabling the feature, I'm adding 3 amps

You can check support of the MSR_TURBO_POWER_CURRENT_LIMIT to alter amps. Try the following MSR read like my W3690 :
rdmsr -a 0x000001ac
83700410
83700410
83700410
83700410
83700410
83700410
83700410
83700410
83700410
83700410
83700410
83700410
You may also have a chance with Thermal Offset which is added or subtracted to the TjMax

It's an architectural register, try to test directly MSR_IA32_TEMPERATURE_TARGET:
rdmsr -a 0x000001a2
651400
651400
651400
651400
651400
651400
651400
651400
651400
651400
651400
651400

Sadly, the TDC option on my cpu is missing and i also cannot read MSR_TURBO_POWER_CURRENT_LIMIT. Anyway, thanks for your help. If you would like to test MSR_OC_MAILBOX function, i'm glad to provide a ssh link to my platform for testing.

0 replies

cyring · 2023-11-15T06:39:52Z

cyring
Nov 15, 2023
Maintainer

#333 (reply in thread)

This is where we tried to program it

0 replies

cyring · 2023-11-15T07:02:37Z

cyring
Nov 15, 2023
Maintainer

13th Generation datasheet vol.2 specifies a bit more about BIOS MAILBOX MMIO Registers, although I have not found the possible commands

https://www.intel.com/content/www/us/en/content-details/743846/13th-generation-intel-core-processors-datasheet-volume-2-of-2.html

0 replies

gundami · 2023-11-16T03:28:17Z

gundami
Nov 16, 2023
Author

Same, i can't find any intel official document about this msr register. But i found a pdf which discribe some details of this register, in 2.2 chapter and below References chapter there is a more detailed table about it.
https://www.usenix.org/system/files/sec20-kenjar.pdf

1 reply

cyring Nov 16, 2023
Maintainer

ITBMT 3.0

cyring · 2024-12-25T06:10:30Z

cyring
Dec 25, 2024
Maintainer

Dev ceased

0 replies

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

CPU Current limit unlock #464

{{title}}

Replies: 12 comments 1 reply

{{title}}

{{title}}

{{editor}}'s edit

{{editor}}'s edit

{{title}}

{{title}}

{{title}}

{{title}}

{{editor}}'s edit

{{editor}}'s edit

{{title}}

{{editor}}'s edit

{{editor}}'s edit

{{title}}

{{title}}

{{editor}}'s edit

{{editor}}'s edit

{{title}}

{{title}}

{{editor}}'s edit

{{editor}}'s edit

{{title}}

{{title}}

Select a reply

CPU Current limit unlock #464

gundami Nov 13, 2023

Replies: 12 comments · 1 reply

cyring Nov 13, 2023 Maintainer

gundami Nov 14, 2023 Author

cyring Nov 14, 2023 Maintainer

cyring Nov 14, 2023 Maintainer

gundami Nov 14, 2023 Author

cyring Nov 14, 2023 Maintainer

cyring Nov 14, 2023 Maintainer

gundami Nov 15, 2023 Author

cyring Nov 15, 2023 Maintainer

cyring Nov 15, 2023 Maintainer

gundami Nov 16, 2023 Author

cyring Nov 16, 2023 Maintainer

cyring Dec 25, 2024 Maintainer

gundami
Nov 13, 2023

Replies: 12 comments 1 reply

cyring
Nov 13, 2023
Maintainer

gundami
Nov 14, 2023
Author

cyring
Nov 14, 2023
Maintainer

cyring
Nov 14, 2023
Maintainer

gundami
Nov 14, 2023
Author

cyring
Nov 14, 2023
Maintainer

cyring
Nov 14, 2023
Maintainer

gundami
Nov 15, 2023
Author

cyring
Nov 15, 2023
Maintainer

cyring
Nov 15, 2023
Maintainer

gundami
Nov 16, 2023
Author

cyring Nov 16, 2023
Maintainer

cyring
Dec 25, 2024
Maintainer