`
+
+### Step 4: Enable SSO in CircuitVerse UI
+
+1. Enable the sso_integration feature flag using Flipper (if not already enabled).
+2. Verify that the SSO login option appears on the login page.
+
+
+
+### Step 5: Test the Integration
+
+1. Log out of CircuitVerse.
+2. Click on the "Login with SSO" button on the CircuitVerse login page.
+3. You should be redirected to the Keycloak login page.
+4. Enter your KeyCloak credentials.
+5. After successful authentication, you should be redirected back to CircuitVerse and logged in.
diff --git a/CircuitVerse-Documentation/docs/chapter3/1introduction.mdx b/CircuitVerse-Documentation/docs/chapter3/1introduction.mdx
new file mode 100644
index 00000000..8e1f4de4
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/1introduction.mdx
@@ -0,0 +1,21 @@
+---
+id: chapter3-introduction
+title: "Introduction"
+description: "Introduction page in Chapter3 of CircuitVerse documentation."
+---
+
+# Introduction
+
+The CircuitVerse simulator includes different sections for building and managing circuit simulations. Watch the below video for a quick demonstration of how you can build and simulate your circuits using different features and workflows available within the CV platform.
+
+
+ VIDEO
+
diff --git a/CircuitVerse-Documentation/docs/chapter3/2understandingcvsimulator.mdx b/CircuitVerse-Documentation/docs/chapter3/2understandingcvsimulator.mdx
new file mode 100644
index 00000000..b2d222e7
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/2understandingcvsimulator.mdx
@@ -0,0 +1,105 @@
+---
+id: chapter3-understandingcvsimulator
+title: "Understandingcvsimulator"
+description: "Understandingcvsimulator page in Chapter3 of CircuitVerse documentation."
+---
+
+# Understanding CircuitVerse Simulator Interface
+
+Figure 3.1 highlights the different sections of the CircuitVerse simulator and Table 3.1 provides a brief description for each section.
+
+
+
+
+ Figure 3.1: Different sections of the CircuitVerse simulator
+
+
+Table 3.1: Different sections of the CircuitVerse simulator
+
+
+
+
+ Display Number
+
+
+ Section Name
+
+
+ Description
+
+
+
+ 1
+ Menu bar
+
+ Displays different options available in the menu bar for managing and
+ creating projects
+
+
+
+ 2
+ Circuit Elements Panel
+ Displays different circuit elements for building the circuit.
+
+
+ 3
+ Properties Panel
+
+ Displays different properties available for the selected circuit element.
+
+
+
+ 4
+ Circuit Tabs
+
+ Displays different circuits and sub-circuits available within the selected
+ project.
+
+
+
+ 5
+ Quick Access Panel
+ Displays task icons for the common CircuitVerse workflows.
+
+
+ 6
+ Timing Diagram
+
+ Displays the level of each input and output after each clock pulse for
+ determining the circuit behavior
+
+
+
+ 7
+ Report System
+
+ Displays a dialog box for reporting an issue or bug to the CircuitVerse
+ support team.
+
+
+
+ 8
+ Canvas
+
+ Display area where the circuit elements can be assembled for building the
+ desired circuit.
+
+
+
+
+While the **CIRCUIT ELEMENTS** panel, **PROPERTIES** panel and the quick access panel can be easily moved around the screen, the **CIRCUIT ELEMENTS** panel and the **PROPERTIES** panel are collapsible panels.
+
+
+
+
+
+Click on the relevant links to learn more about a given section:
+
+- [Menu Bar](/chapter3/menubar.mdx)
+- [Circuit Elements Panel](/chapter3/circuitelements.mdx)
+- [Properties Panel](/chapter3/properties.mdx)
+- [Circuit Tabs](/chapter3/circuittabs.mdx)
+- [Quick Access Panel](/chapter3/quickaccesspanel.mdx)
+- [Canvas](/chapter3/canvas.mdx)
+- [Report System](/chapter3/reportsystem.mdx)
+- [Multi-bit Wires (Buses)](/chapter3/wires.mdx)
diff --git a/CircuitVerse-Documentation/docs/chapter3/canvas.mdx b/CircuitVerse-Documentation/docs/chapter3/canvas.mdx
new file mode 100644
index 00000000..89770c1b
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/canvas.mdx
@@ -0,0 +1,9 @@
+---
+id: chapter3-canvas
+title: "Canvas"
+description: "Canvas page in Chapter3 of CircuitVerse documentation."
+---
+
+# Canvas
+
+Canvas is the large empty space available in the middle of the simulator for building the desired circuit. Circuit elements can be dragged from the **CIRCUIT ELEMENTS** panel into the Canvas and arranged to build the circuit. Each circuit element has its own properties, and the relevant properties can be edited using the **PROPERTIES** panel. As the design matures, the user can conveniently move, rearrange or rotate components on the drawing canvas, create subcircuits for managing sophisticated designs or add annotation elements for improved understanding.
diff --git a/CircuitVerse-Documentation/docs/chapter3/circuitelements.mdx b/CircuitVerse-Documentation/docs/chapter3/circuitelements.mdx
new file mode 100644
index 00000000..2c11b234
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/circuitelements.mdx
@@ -0,0 +1,18 @@
+---
+id: chapter3-circuitelements
+title: "Circuitelements"
+description: "Circuitelements page in Chapter3 of CircuitVerse documentation."
+---
+
+# Circuit Elements Panel
+
+CircuitVerse offers a vast library of circuit elements (refer Figure 3.12) for building different types of digital circuits. Each circuit element has its own properties, and the relevant properties can be edited using the PROPERTIES panel. Chapter 4 shares a detailed description of the different customizable attributes of these circuit elements.
+
+
+
+
+
+ Figure 3.12: Vast library of circuit elements for building different types
+ of digital circuits
+
+
diff --git a/CircuitVerse-Documentation/docs/chapter3/circuittabs.mdx b/CircuitVerse-Documentation/docs/chapter3/circuittabs.mdx
new file mode 100644
index 00000000..a315ecf0
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/circuittabs.mdx
@@ -0,0 +1,43 @@
+---
+id: chapter3-circuittabs
+title: "Circuittabs"
+description: "Circuittabs page in Chapter3 of CircuitVerse documentation."
+---
+
+# Circuit Tabs
+
+Similar to a web browser navigation bar, the circuit tabs section lists the different available circuits for the selected project. By default, every project must have at least one main circuit in the circuit tab section. If the user tries to delete the main circuit without adding any main circuit, the simulator displays an error as shown in Figure 3.16.
+
+
+
+
+ Figure 3.16
+
+
+## Add Circuit Tabs
+
+As the complexity of the circuit design grows (refer Figure 3.17), different selections listed in the Circuit drop-down menu (refer Figure 3.18) can be used to add circuit tabs, or insert as a subcircuit within another circuit tab.
+
+> TIP: Cross-project copy and paste is supported to include whole or parts of circuits across different circuit tabs.
+
+
+
+
+ Figure 3.17
+
+
+
+
+
+ Figure 3.18
+
+
+## Rename Circuit Tabs
+
+While building larger circuits using subcircuits, the circuit tabs can be renamed. Navigate to the PROPERTIES panel. Edit the Circuit parameter to rename the circuit tab as shown in Figure 3.19.
+
+
+
+
+ Figure 3.19
+
diff --git a/CircuitVerse-Documentation/docs/chapter3/menubar.mdx b/CircuitVerse-Documentation/docs/chapter3/menubar.mdx
new file mode 100644
index 00000000..34b7ad0f
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/menubar.mdx
@@ -0,0 +1,301 @@
+---
+id: chapter3-menubar
+title: "Menubar"
+description: "Menubar page in Chapter3 of CircuitVerse documentation."
+---
+
+# Menu Bar
+
+The menu bar (as shown in Figure 3.2) contains different labels for the different workflows to create and analyse their digital design simulations. Table 3.2 provides a quick description of the different labels available in the CircuitVerse menu bar.
+
+
+
+
+ Figure 3.2
+
+
+Table 3.2: Brief description of different labels available in the CircuitVerse simulator menu bar
+
+
+
+
+ Name
+
+
+ Description
+
+
+
+ Project
+
+ Lists different workflows for creating, opening and managing CircuitVerse
+ simulation files.
+
+
+
+ Circuit
+
+ Lists different workflows for creating new circuits and inserting
+ sub-circuits.
+
+
+
+ Tools
+
+ Lists different tools available within the simulator for creating and
+ analyzing a circuit simulation.
+
+
+
+ Help
+ Lists different user assistance resources while using CircuitVerse.
+
+
+
+## Project
+
+CircuitVerse provides different options for creating and managing CircuitVerse projects online or offline. Table 3.3 shares a brief description of the different options available in the **Project** drop-down menu (refer Figure 3.3).
+
+
+
+
+ Figure 3.3
+
+
+Table 3.3: Brief description of different selections available in the Project drop-down menu
+
+
+
+
+ Name
+
+
+ Description
+
+
+
+ New Project
+ Opens a new project file for building a live circuit
+
+
+ Save Online
+
+ Saves the displayed project online on the user dashboard. Users must be
+ logged into the CircuitVerse platform to save the project online.
+
+
+
+ Save Offline
+
+ Saves the displayed project in the browser’s local storage even if the
+ user is not logged into the CircuitVerse platform.
+
+
+
+ Open Offline
+ Opens a project from the browser’s local storage
+
+
+ Clear Project
+
+ Clears the content (including all the circuit tabs) of the working project
+ file.
+
+
+
+ Recover Project
+
+ Recovers the content of the last project that the user was working on.
+
+
+
+ Preview Circuit
+
+ Displays the full circuit view of the displayed image. The simulator zooms
+ in or out of the current view so that the circuit image fits the entire
+ screen.
+
+
+
+
+While saving projects online, users are directed to the **Edit Project** page for sharing more details about the project (refer Figure 3.4).
+
+
+
+
+ Figure 3.4
+
+
+Watch this video for more information on the different fields that can be used for sharing more information about the project.
+
+
+
+
+
+## Circuit
+
+As the circuit design grows, the **Circuit** drop-down menu (refer Figure 3.5) lists different options for managing the design structure. Table 3.4 further shares a brief description of the different options.
+
+
+
+
+ Figure 3.5
+
+
+Table 3.4: Brief description of different selections available in the Circuit drop-down menu
+
+
+
+
+ Name
+
+
+ Description
+
+
+
+ New Circuit+
+ Adds a new tab in the circuit tab bar
+
+
+ New Verilog Module
+ Inserts a circuit comprising of Verilog module
+
+
+ Insert Subcircuit
+
+ Inserts a circuit layout generated using CircuitVerse simulator as a
+ subcircuit in another circuit tab
+
+
+
+
+Besides adding multiple circuit tabs within a project, circuit tabs can also be nested within other circuit tabs for organizing a hierarchical design. A subcircuit is a modular functional block that delivers a single function within a given design. Additionally, a subcircuit generated using a Verilog module can also be inserted.
+
+> NOTE: Unlike CircuitVerse simulations, the circuit generated using a Verilog module can be simulated as a subcircuit only.
+
+## Tools
+
+Table 3.5 shares a brief description of the different options available in the **Tools** drop-down menu (refer Figure 3.6).
+
+
+
+
+ Figure 3.6
+
+
+Table 3.5: Brief description of different selections available in the **Tools** drop-down menu
+
+
+
+
+ Name
+
+
+ Description
+
+
+
+ Combinational Analysis
+ Converts a truth table data into a circuit
+
+
+ Hex-Bin-Dec Converter
+ Converts a hex number into its equivalent binary and decimal number
+
+
+ Download Image
+
+ Downloads the displayed circuit design in different formats and
+ resolutions
+
+
+
+ Themes
+
+ Displays different colour schemes for defining the aesthetics of the
+ CircuitVerse simulator interface
+
+
+
+ Custom Shortcut
+
+ Displays different keyboard shortcuts for different tasks within
+ CircuitVerse simulator
+
+
+
+ Export Verilog
+
+ Generates and exports a Verilog file for the displayed circuit design
+
+
+
+
+## Combinational Analysis Tool
+
+The Combinational Analysis tool available within the CircuitVerse simulator generates a circuit using combinational analysis or a boolean function (refer Figure 3.7). A truth table is then populated to construct the final circuit using different different gates and circuit elements.
+
+> NOTE: If the user generates the circuit by entering a boolean function, then the truth table is auto populated else the user must manually set the values.
+
+
+
+
+
+ Figure 3.7: Besides building a circuit using different circuit elements, the
+ combinational analysis tool can also be used for generating a circuit using
+ combinational analysis or a boolean function
+
+
+
+The circuit's inputs and outputs will be displayed in top-down and left-right order corresponding to how they were identified in the **Boolean Logic Table** popup window. Watch the below video to learn more about this tool.
+
+
+
+## Hex-Bin-Dec Converter
+
+The Hex-Bin-Dec Converter tool (refer Figure 3.8) converts a given binary number into its equivalent decimal, octal or hexadecimal value. Alternatively, a user can also generate a binary value from different available formats.
+
+
+
+
+
+ Figure 3.8: Use the dec-bin-hex convertool to convert binary data into
+ different formats
+
+
+
+## Themes
+
+Different themes have been included that change the colors of the CircuitVerse simulator user interface (UI) while maintaining the contrast across different UI elements. Refer Figure 3.9.
+
+
+
+
+ Figure 3.9: Different CircuitVerse simulator UI themes
+
+
+## Custom Shortcuts
+
+The Custom Shortcuts window displays different shortcuts for common user operations. As required, each of the available key shortcuts can be edited for a user preference and restored back to its default value. Refer Figure 3.10.
+
+
+
+
+ Figure 3.10: Different key shortcuts available within CircuitVerse
+
+
+## Export Verilog
+
+Every circuit simulation project created within CircuitVerse can be exported as a Verilog code. As Figure 3.11 illustrates, the code file can then either be downloaded on the machine as a verilog file or tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7.
+
+> NOTE: This is an experimental module and some changes may be needed for the code to work.
+
+
+
+
+
+ Figure 3.11: Verilog code can be downloaded on the machine or tested on the
+ EDA Playground
+
+
diff --git a/CircuitVerse-Documentation/docs/chapter3/properties.mdx b/CircuitVerse-Documentation/docs/chapter3/properties.mdx
new file mode 100644
index 00000000..cd35999f
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/properties.mdx
@@ -0,0 +1,194 @@
+---
+id: chapter3-properties
+title: "Properties"
+description: "Properties page in Chapter3 of CircuitVerse documentation."
+---
+
+# Properties Panel
+
+Each circuit element has some properties associated with itself which are displayed in the **PROPERTIES **panel. Besides including different parameters for creating multi-bit circuits, it also includes parameters for annotation. the circuit schematic can be annotated by:
+
+- Adding labels across different nodes.
+- Including text boxes for displaying the version number, date, amendments and different group members involved.
+- Adding rectangular boxes for highlighting different sections for complex designs.
+
+While Figure 3.13 displays the properties associated with an AND gate, Table 3.7 lists the different properties available within the CircuitVerse simulator for different circuit elements.
+
+
+
+
+ Figure 3.13
+
+
+Table 3.7: Brief description of the different properties available for different circuit elements
+
+
+
+
+ Property Parameter
+
+
+ Description
+
+
+
+ Project
+ Defines the project name that will be displayed in the menu bar
+
+
+ Circuit
+ Identifies the circuit tab that the user is currently working on.
+
+
+ Clock Time
+
+ Toggles the output value at a regular interval. While the default value is
+ 500 ms, the clock interval can be increased or decreased using the
+ stepper.
+
+
+
+ BitWidth
+
+ Specifies the bit width associated with the selected input or output
+ circuit element. The bit width numeric stepper changes the bit width size
+ from 1 to 32.
+
+
+
+ Delay
+
+ Displays a delay slider to add propagation delays.The delays are
+ simulated; but they are virtual and therefore not rendered.
+
+
+
+ Font Size
+
+ Displays a stepper to increase or decrease the font size. The default
+ value is 14.
+
+
+
+ Input Size
+ Specifies the input size of the selected circuit element.
+
+
+ Label
+
+ Adds a label for the selected element. For most of the circuit elements,
+ the label can be further positioned using the
+ Label Direction property.
+
+
+
+ Label Direction
+
+ Sets the position of the label for the relevant circuit element. Users can
+ choose the desired label direction value from the drop-down menu.
+
+
+
+ Pin Length
+ Displays a slider to set the pin length of the selected element.
+
+
+ Direction
+
+ Sets the direction of the selected element.*
+
+
+
+ Orientation
+
+ Sets the pin direction of the selected element.*
+
+
+
+ Buffer Size
+ Displays a slider to set the buffer size. Minimum value is 20.
+
+
+ Columns
+
+ Displays a slider to set the number of columns for the selected element.
+
+
+
+ Rows
+
+ Displays a slider to set the number of rows for the selected element.
+
+
+
+ TestBench Name
+ Displays the name of the test bench for the selected element.
+
+
+
+> TIP\* : The direction/orientation of the circuit element can be changed using the arrow keys.
+
+## Edit Circuit Layout
+
+As shown in Figure 3.14, the **Edit Layout **button available on the **PROPERTIES **panel converts the circuit into a black box. The circuit elements and the relevant connections are hidden whereas the input and output pins are displayed (in the same order as displayed in the main circuit ).
+
+
+
+
+ Figure 3.14
+
+
+As required, a user can use the **LAYOUT ELEMENTS** panel to add any circuit elements inside the subcircuit (black box), and the **LAYOUT** panel to edit the layout of the circuit. Refer Figure 3.15. Table 8 provides a brief description of the different settings available on the **LAYOUT** panel.
+
+> NOTE: Circuit layout must be edited before inserting a circuit or completing the wiring connections. If the node positions within the circuit layout are edited after making the wiring connections, then some of the wiring connections across different nodes or ports in the integrated circuit schematic may be lost.
+
+> TIP: Make all the necessary changes within the circuit layout prior to the wiring connections.
+
+
+
+
+ Figure 3.15
+
+
+Table 3.8: Brief description of the different settings available on the **LAYOUT** panel
+
+
+
+
+ Setting
+
+
+ Description
+
+
+
+ Width
+
+ Displays a numeric stepper to manage the width of the circuit layout.
+
+
+
+ Height
+
+ Displays a numeric stepper to manage the height of the circuit layout.
+
+
+
+ Reset all nodes
+ Resets the nodes to their default position.
+
+
+ Title Enabled
+
+ Displays or hides the title of the subcircuit. By default, the title is
+ displayed for each circuit layout.
+
+
+
+ Title Position
+
+ Positions the title at a desired location using the up, down, right and
+ left arrows.
+
+
+
diff --git a/CircuitVerse-Documentation/docs/chapter3/quickaccesspanel.mdx b/CircuitVerse-Documentation/docs/chapter3/quickaccesspanel.mdx
new file mode 100644
index 00000000..81fbaf24
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/quickaccesspanel.mdx
@@ -0,0 +1,15 @@
+---
+id: chapter3-quickaccesspanel
+title: "Quickaccesspanel"
+description: "Quickaccesspanel page in Chapter3 of CircuitVerse documentation."
+---
+
+# Quick Access Panel
+
+The quick access panel (refer Figure 3.20) provides access to common workflows within the CircuitVerse simulator. While working on the circuit, hover the mouse over the icons for a brief description. As needed, the tool bar can be conveniently moved around the canvas or positioned in the menu bar.
+
+
+
+
+ Figure 3.20
+
diff --git a/CircuitVerse-Documentation/docs/chapter3/reportsystem.mdx b/CircuitVerse-Documentation/docs/chapter3/reportsystem.mdx
new file mode 100644
index 00000000..bbaf19bc
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/reportsystem.mdx
@@ -0,0 +1,24 @@
+---
+id: chapter3-reportsystem
+title: "Reportsystem"
+description: "Reportsystem page in Chapter3 of CircuitVerse documentation."
+---
+
+# Report System
+
+
+
+
+ Figure 3.21
+
+
+A user can report an unexpected behavior frequently using **Report an issue** button displayed in the bottom right hand corner of the screen (refer Figure 3.21). For effective bug reporting, the description field must include detailed information for reproducing the issue. Some of the good-to-have information include:
+
+- Steps to reproduce the bug
+- Expected result of the application
+- Actual result of the application
+- Supporting artifacts like screenshots or videos
+
+Alternatively, any ideas, feature requests or bug fixes can be submitted on GitHub at https://github.com/CircuitVerse/CircuitVerse/issues/new/choose.
+
+> TIP: Before reporting an issue, submit a query on the CircuitVerse Forum (https://circuitverse.org/forum) to learn more about similar experiences or known workarounds.
diff --git a/CircuitVerse-Documentation/docs/chapter3/wires.mdx b/CircuitVerse-Documentation/docs/chapter3/wires.mdx
new file mode 100644
index 00000000..0285fcaa
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter3/wires.mdx
@@ -0,0 +1,65 @@
+---
+id: chapter3-wires
+title: "Wires"
+description: "Wires page in Chapter3 of CircuitVerse documentation."
+---
+
+# Multi-bit Wires (Buses)
+
+Different circuit elements can be connected by clicking on the output of one gate or port, and dragging the mouse to the input of the next one. While connecting two elements, the wire rubber bands around an angle (refer Figure 3.22). However, if any input of any circuit element is not connected within the circuit, it does not affect the circuit behavior.
+
+
+
+
+ Figure 3.22
+
+
+## Understanding Wire Colors
+
+When a wire connects two circuit elements, the CircuitVerse simulator displays different wire colors (refer Figure 3.22) to indicate the bit width status of the wire. As the circuits become more complex, users can study the wire colors to troubleshoot or analyse their circuit behavior in CircuitVerse. Table 3.9 shares a description of the bit width status of the wire for different wire colors.
+
+Table 3.9: Understanding wire colors for different bit width values of a given wire
+
+
+
+
+ Wire Color
+
+
+ Description
+
+
+
+ Blue
+ The bit width value that the wire is carrying is not known.
+
+
+ Dark green
+ The wire is carrying a one-bit 0 value.
+
+
+ Bright green
+ The wire is carrying a one-bit 1 value.
+
+
+ Black
+
+ The wire is carrying a multi-bit value but some or all of the bits may not
+ be specified.
+
+
+
+ Red
+ The wire is carrying an illegal or unknown value.
+
+
+
+## Creating Multi-bit Wires
+
+Most of the circuit elements in CircuitVerse have a bit width value associated with it. While Figure 3.23 illustrates multibit wires being used for splitting and combining multi-bit data into equal and unequal parts using splitters, different circuit elements include different attributes within the **PROPERTIES** panel to customize the bit widths of their inputs and outputs.
+
+
+
+
+ Figure 3.23
+
diff --git a/CircuitVerse-Documentation/docs/chapter4/1introduction.mdx b/CircuitVerse-Documentation/docs/chapter4/1introduction.mdx
new file mode 100644
index 00000000..0a136f6f
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter4/1introduction.mdx
@@ -0,0 +1,35 @@
+---
+id: chapter4-introduction
+title: "Introduction"
+description: "Introduction page in Chapter4 of CircuitVerse documentation."
+---
+
+# Circuit Elements Library
+
+CircuitVerse includes a vast library of circuit elements for building circuits (refer Figure 4.1).
+
+
+
+
+
+ Figure 4.1: Different circuit elements are available within the CV simulator
+ for building circuits
+
+
+
+This section includes:
+
+- A detailed description of each circuit element.
+- Different tips and tricks for using a circuit element.
+- Different property attributes that can be customized in the **PROPERTIES** panel.
+- Live circuits (for some of the circuit elements) to demonstrate the circuit element behavior.
+
+To learn more about a given circuit element, click on the relevant circuit element category listed below:
+
+1. [Input](/chapter4/2input.mdx)
+2. [Output](/chapter4/3output.mdx)
+3. [Gates](/chapter4/4gates.mdx)
+4. [Decoders & Plexers](/chapter4/5muxandplex.mdx)
+5. [Sequential Elements](/chapter4/6sequentialelements.mdx)
+6. [Annotation](/chapter4/7annotation.mdx)
+7. [Misc](/chapter4/8misc.mdx)
diff --git a/CircuitVerse-Documentation/docs/chapter4/2input.mdx b/CircuitVerse-Documentation/docs/chapter4/2input.mdx
new file mode 100644
index 00000000..1020e4ae
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter4/2input.mdx
@@ -0,0 +1,168 @@
+---
+id: chapter4-input
+title: "Input"
+description: "Input page in Chapter4 of CircuitVerse documentation."
+---
+
+# Input
+
+Circuitverse features different input elements listed below:
+
+1. [Input](#input)
+2. [Button](#button)
+3. [Power](#power)
+4. [Ground](#ground)
+5. [ConstantVal](#constantval)
+6. [Stepper](#stepper)
+7. [Counter](#counter)
+
+## Input
+
+The **Input** circuit element can have two input states - HIGH or LOW.
+
+Property attributes that can be customized within the **PROPERTIES** panel include **BitWidth**.
+
+You can verify the behavior of the **Input** circuit element (by clicking on the circuit element once) in the live circuit embedded below:
+
+
+
+## Button
+
+The **Button** circuit element is a simple push button mechanism for controlling the output of the circuit.
+
+- HIGH when pressed
+- LOW when released
+
+You can verify the behavior of the **Button** circuit element in the live circuit embedded below:
+
+
+
+
+
+## Power
+
+The **Power** circuit element in the circuit design is always in a HIGH state. This component should be used when there is a need for the input to be always HIGH.
+
+VIDEO
+
+As the above example explains, the value of the **ConstantVal** circuit element can be changed by double-clicking the component and entering the value in the prompt.
+
+## Stepper
+
+The value of the **Stepper** circuit element can either be increased or decreased by pressing the "+" key or "-" key on the keyboard to increase or decrease the value.
+
+You can verify the behavior of the **Stepper** circuit element in the live circuit embedded below:
+
+
+
+## Random
+
+The **Random** circuit element generates a random value in the range (0, maxvalue) every time it receives a HIGH signal from the clock. It has 3 ports in total:
+
+- **Max Value**: input, maximum value generated.
+- **Clock**: input clock element. Every time the clock receives a HIGH input, the random element generates a number.
+- **Random Value**: output, the number generated.
+
+The value is also displayed in decimal notation on the random element.
+
+You can verify the behavior of the **Random** circuit element in the live circuit embedded below:
+
+
+
+## Counter
+
+The **Counter** circuit element is a binary counter that runs from zero to a specified maximum value. It has five ports in total:
+
+- **Max Value**: input, maximum value that the counter will reach.
+- **Clock**: input clock element, every time the clock gets HIGH the counter increments by one.
+- **Reset**: input, when HIGH it resets the counter to zero.
+- **Zero**: output, it's HIGH when the counter is zero.
+- **Value**: output, value of the counter in binary.
+
+The value is also displayed in decimal notation on the counter element.
+
+You can verify the behavior of the Counter circuit element in the live circuit embedded below:
+
+
diff --git a/CircuitVerse-Documentation/docs/chapter4/3output.mdx b/CircuitVerse-Documentation/docs/chapter4/3output.mdx
new file mode 100644
index 00000000..0336891d
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter4/3output.mdx
@@ -0,0 +1,200 @@
+---
+id: chapter4-output
+title: "Output"
+description: "Output page in Chapter4 of CircuitVerse documentation."
+---
+
+# Output
+
+CircuitVerse features different output elements listed below:
+
+1. [Output](#output)
+2. [Digital LED](#digital-led)
+3. [VariableLED](#variableled)
+4. [RGBLED](#rgbled)
+5. [SquareRGBLED](#squarergbled)
+6. [HexDisplay](#hexdisplay)
+7. [SevenSegDisplay](#sevensegdisplay)
+8. [SixteenSegDisplay](#sixteensegdisplay)
+
+## Output
+
+When the **Output** circuit element is connected to another circuit element, it displays the relevant output in binary form.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth**
+
+You can verify the behavior of the **Output** circuit element in the live circuit embedded below:
+
+
+
+## Digital LED
+
+The **Digital LED** element switches between on and off depending on the input applied to it.
+
+- Input of `1` turns on the LED
+- Input of `0` turns off the LED.
+
+The digital LED does not recognize inputs of a length other than one bit. For your project, if the color must be changed based on the applied input, use the [RGB LED element](https://docs.circuitverse.org/#/outputs?id=rgb-led).
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Color\***
+>
+> \*_Color of a LED can be changed using color name, HEX color codes, RGB and HSL values_
+
+You can verify the behavior of the **Digital LED** circuit element in the live circuit embedded below:
+
+
+
+## VariableLED
+
+The **variableLED** element changes between 256 intensities based on an 8-bit input. It has a:
+
+- Maximum intensity when the input applied is `11111111`
+- Zero intensity when the input applied is `00000000`.
+
+You can verify the behavior of the **variableLED** circuit element in the live circuit embedded below:
+
+
+
+## RGBLED
+
+Unlike the **digitalLED or variableLED** circuit elements, the **RGBLED** element can display a wide variety of colors. It takes three 8-bit inputs which describe the intensity of red, green, and blue color respectively.
+
+> TIP: Use a [color picker](https://htmlcolorcodes.com/color-picker/) to find the corresponding R, G, and B values and then use a [decimal-to-binary converter](https://codebeautify.org/decimal-binary-converter) to find the corresponding 8-bit value that must be entered for each input.
+
+You can verify the behavior of the **RGBLED** circuit element in the live circuit embedded below:
+
+
+
+## SquareRGBLED
+
+While the **SquareRGBLED** works similarly to the **RGBLED**, the **SquareRGBLED** differs in its shape and includes pin lengths that can be customized in the **PROPERTIES** panel. These additional features make **SquareRGBLEDs** ideal for simulating arrays of pixels.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Pin Length**
+
+The live circuit embedded below illustrates how an array of pixels may be programmed to display an image. The circuit design includes a LED buffer subcircuit that manages the circuitry controlling the LEDs. The ability to vary the pin length of the square RGB LED element makes the design clean and easy to read. To make the design more comprehensible, the pins for different square LEDs must remain in the same vertical order as the LEDs themselves (i.e. the top pins must correspond to the top LED).
+
+
+
+## HexDisplay
+
+The **HexDisplay** is more simple to use than the** SevenSegDisplay** and **SixteenSegDisplay **circuit elements. Since it takes a 4-bit input and can display integers 1 through 9 and the letters A through F, there is less room for customization.
+
+The input bits do not control the individual segments ( as it is not possible to control six segments with only four bits). The hex display simply recognizes the integer/letter that a given input corresponds to and displays the character. The display character thus does not need to be programmed.
+
+You can verify the behavior of the **HexDisplay** circuit element in the live circuit embedded below:
+
+
+
+## SevenSegDisplay
+
+The **SevenSegDisplay** behaves similar to a **HexDisplay**, but it takes an 8-bit input rather than a 4-bit input––making it more customizable. It takes in eight inputs and displays an output, an integer from 1 to 9. As Figure 4.2 elucidates, the top four inputs correspond to the middle, top left, top, and top right segments from left to right respectively. The bottom four inputs correspond to the bottom left, bottom, bottom right, and decimal segments from left to right respectively.
+
+
+
+
+ Figure 4.2: Pin description of SevenSegDisplay
+
+
+You can verify the behavior of the **SevenSegDisplay** circuit element in the live circuit embedded below:
+
+
+
+Watch [this video tutorial](https://www.youtube.com/watch?v=EqxCBW0lMVQ) to learn more about how to use this circuit element in a circuit.
+
+## SixteenSegDisplay
+
+The **SixteenSegDisplay** takes two inputs and a total of 17 bits: 16 bits in the top input and 1 bit in the bottom input. Each of the 16 bits applied to the top input corresponds to a certain segment in the sixteen segment display. The single bit applied to the bottom input controls the decimal point.
+
+You can verify the behavior of the **SixteenSegDisplay** circuit element in the live circuit embedded below:
+
+
+
+As opposed to the **HexDisplay** and **SevenSegDisplay** circuit elements, the main advantage of using a **SixteenSegDisplay** is that multiple segments can be used to create numbers and letters. However, it requires double the input of the **SevenSegDisplay** and quadruple the input of the **HexDisplay**.
diff --git a/CircuitVerse-Documentation/docs/chapter4/4gates.mdx b/CircuitVerse-Documentation/docs/chapter4/4gates.mdx
new file mode 100644
index 00000000..9a314e61
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter4/4gates.mdx
@@ -0,0 +1,246 @@
+---
+id: chapter4-gates
+title: "Gates"
+description: "Gates page in Chapter4 of CircuitVerse documentation."
+---
+
+# Gates
+
+CircuitVerse features the following gates in the circuit elements library:
+
+- [Gates](#gates)
+ - [AND Gate](#and-gate)
+ - [OR Gate](#or-gate)
+ - [NOT Gate](#not-gate)
+ - [XOR Gate](#xor-gate)
+ - [NAND Gate](#nand-gate)
+ - [NOR Gate](#nor-gate)
+ - [XNOR Gate](#xnor-gate)
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Bit Width, Input Size, Direction**
+
+> TIP: Direction of any gate can be changed within the CircuitVerse simulator by either using the up, down, right, left arrow keys or by changing the **Direction** property parameter in the **PROPERTIES** panel.
+
+Each of the gates included in the CircuitVerse library can be customized for multiple input size and multiple bitwidth. Users can create:
+
+- Multi-input gate by changing the **Input Size** property parameter in the **PROPERTIES** panel. You can verify the behavior of a multi-input **AND gate** in the live circuit embedded below:
+
+
+
+- Multi-bitwidth AND gate by changing the **BitWidth** property parameter in the **PROPERTIES** panel. You can verify the behavior of a multi-bitwidth **AND gate** in the live circuit embedded below:
+
+
+
+## AND Gate
+
+AND gate gives a HIGH output only if all input values are HIGH. Refer Table 4.25.
+
+Table 2.5: Two-input AND gate truth table
+
+| Input 1 | Input 2 | Output |
+| ------- | ------- | ------ |
+| 0 | 0 | 0 |
+| 0 | 1 | 0 |
+| 1 | 0 | 0 |
+| 1 | 1 | 1 |
+
+You can verify the behavior of the **AND gate** circuit element in the live circuit of a two-input AND gate embedded below:
+
+
+
+## OR Gate
+
+OR gate produces a HIGH output only if any of the input values are HIGH. Refer Table 4.26.
+
+Table 2.6: Two-input OR gate truth table
+
+| Input 1 | Input 2 | Output |
+| ------- | ------- | ------ |
+| 0 | 0 | 0 |
+| 0 | 1 | 1 |
+| 1 | 0 | 1 |
+| 1 | 1 | 1 |
+
+You can verify the behavior of an **OR gate** circuit element in the live circuit embedded below:
+
+
+
+## NOT Gate
+
+NOT gate inverts the input as an output. It is also known as an inverter. Refer Table 4.27.
+
+Table 4.27: NOT gate truth table
+
+| Input | Output |
+| ----- | ------ |
+| 0 | 1 |
+| 1 | 0 |
+
+You can verify the behavior of an **NOT gate** circuit element in the live circuit embedded below:
+
+
+
+## XOR Gate
+
+XOR gate produces a HIGH output only if both inputs aren't the same. Refer Table 4.28.
+
+Table 4.28: Two-input XOR gate truth table
+
+| Input 1 | Input 2 | Output |
+| ------- | ------- | ------ |
+| 0 | 0 | 0 |
+| 0 | 1 | 1 |
+| 1 | 0 | 1 |
+| 1 | 1 | 0 |
+
+You can verify the behavior of an **XOR gate** circuit element in the live circuit embedded below:
+
+
+
+## NAND Gate
+
+NAND gate, a combination of an AND gate and a NOT gate connected together in series, produces the inverted output of an AND gate––produces a LOW output when all the inputs are HIGH. Refer Table 4.29.
+
+Table 4.29: Two-input NAND gate truth table
+
+| Input 1 | Input 2 | Output |
+| ------- | ------- | ------ |
+| 0 | 0 | 1 |
+| 0 | 1 | 1 |
+| 1 | 0 | 1 |
+| 1 | 1 | 0 |
+
+You can verify the behavior of an **NAND gate** circuit element in the live circuit embedded below:
+
+
+
+## NOR Gate
+
+NOR gate inverts the output of an OR gate. In other words, it only goes HIGH when all the inputs are LOW. Refer Table 4.30.
+
+Table 4.30: Two-input NOR gate truth table
+
+| Input 1 | Input 2 | Output |
+| ------- | ------- | ------ |
+| 0 | 0 | 1 |
+| 0 | 1 | 0 |
+| 1 | 0 | 0 |
+| 1 | 1 | 0 |
+
+You can verify the behavior of an **NOR gate** circuit element in the live circuit embedded below:
+
+
+
+## XNOR Gate
+
+XNOR gate inverts the output of an XOR gate––it only goes HIGH if both the inputs are the same. Refer Table 4.31.
+
+Table 4.31: Two-input XNOR gate truth table
+
+| Input 1 | Input 2 | Output |
+| ------- | ------- | ------ |
+| 0 | 0 | 1 |
+| 0 | 1 | 0 |
+| 1 | 0 | 0 |
+| 1 | 1 | 1 |
+
+You can verify the behavior of an **XNOR gate** circuit element in the live circuit embedded below:
+
+
diff --git a/CircuitVerse-Documentation/docs/chapter4/5muxandplex.mdx b/CircuitVerse-Documentation/docs/chapter4/5muxandplex.mdx
new file mode 100644
index 00000000..0f93ef44
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter4/5muxandplex.mdx
@@ -0,0 +1,690 @@
+---
+id: chapter4-muxandplex
+title: "Muxandplex"
+description: "Muxandplex page in Chapter4 of CircuitVerse documentation."
+---
+
+# Decoders & Plexers
+
+CircuitVerse features the following circuit elements in this category:
+
+1. [Multiplexer](#multiplexer)
+2. [Demultiplexer](#demultiplexer)
+3. [BitSelector](#bitselector)
+4. [Most Significant Bit (MSB) Detector](#most-significant-bit-msb-detector)
+5. [Least Significant Bit (LSB) Detector](#least-significant-bit-lsb-detector)
+6. [Priority Encoder](#priority-encoder)
+7. [Decoder](#decoder)
+8. [Parity Generator & Parity Detector](#parity-generator--parity-detector)
+
+## Multiplexer
+
+A **Multiplexer** selectively passes only one of the inputs provided to it using a control signal. The number of inputs is always a power of 2. If there are N control bits, then there can be a maximum of 2^N inputs.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth, Control Signal Size**
+
+Consider a 2 to 1 multiplexer that takes two single-bit inputs (T1 and T2), a single-bit control signal (S) and has an output (Out). Using Table 4.1, you can verify the behavior of a 2 to 1 multiplexer.
+
+Table 4.1: Truth table of a 2 to 1 multiplexer
+
+
+
+ S Out
+
+ 0
+ T1
+
+
+ 1
+ T2
+
+
+
+
+
+Using Table 4.2, you can verify the behavior of the **Multiplexer** circuit element in the live circuit of a 4 to 1 multiplexer embedded below:
+
+Table 4.2: Truth table of a 4 to 1 multiplexer
+
+
+
+ S1 S0 Out
+
+ 0
+ 0
+ T1
+
+
+ 0
+ 1
+ T2
+
+
+ 1
+ 0
+ T3
+
+
+ 1
+ 1
+ T4
+
+
+
+
+
+## Demultiplexer
+
+A **Demultiplexer** takes an input and passes it to only one of outputs using a control signal. The number of outputs is always a power of 2. If there are N control bits, we can choose to pass the output to any one of the 2^N output lines.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth, Control Signal Size**
+
+In the live circuit embedded below, a 1 to 2 demultiplexer takes in a single-bit input (T), a single-bit control signal (S) and two single-bit outputs (O1 and O2). Table 4.3 displays the truth table of a 1 to 2 demultiplexer.
+
+Table 4.3: Truth table of a 1 to 2 demultiplexer
+
+
+
+ S O1 O2
+
+ 0
+ T
+ 0
+
+
+ 1
+ 0
+ T
+
+
+
+
+
+In another example of a live circuit embedded below, a 1 to 4 demultiplexer takes in a three-bit input and a two-bit control signal. Table 4.4 displays the truth table of a 1 to 4 demultiplexer.
+
+Table 4.4: Truth table of a 1 to 4 demultiplexer
+
+
+
+ S1 S0 O1 O2 O3 O4
+
+ 0
+ 0
+ T
+ 0
+ 0
+ 0
+
+
+ 0
+ 1
+ 0
+ T
+ 0
+ 0
+
+
+ 1
+ 0
+ 0
+ 0
+ T
+ 0
+
+
+ 1
+ 1
+ 0
+ 0
+ 0
+ T
+
+
+
+
+
+## BitSelector
+
+As its name suggests, the **BitSelector** circuit element takes a single or multi-bit input and outputs the bit that must be isolated using a single or multi-bit select line. The select line value indicates the specific bit that must be isolated within its body in decimal form.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth, Selector Bit Width**
+
+In the live circuit embedded below, a **BitSelector** with a four-bit input is used. Each of its bits can be addressed separately as T3, T2, T1, T0 (from most significant to least significant). It also includes a two-bit select line (S1 and S0) and a single-bit output (Out). Table 4.5 displays the truth table of a four-bit BitSelector.
+
+Table 4.5: Truth table of a four-bit bit selector
+
+
+
+ S1 S0 Out
+
+ 0
+ 0
+ T0
+
+
+ 0
+ 1
+ T1
+
+
+ 1
+ 0
+ T2
+
+
+ 1
+ 1
+ T3
+
+
+
+
+
+## Most Significant Bit (MSB) Detector
+
+The **Most Significant Bit (MSB)** detector circuit element outputs the bit position of the most significant bit of the input. In other words, it outputs the bit position of the rightmost bit. An enable output is also provided to show if the MSB detector is active. The bit position of the MSB is also shown in decimal form within the body of the MSB detector.
+
+You can verify the behavior of the **Most Significant Bit (MSB)** detector circuit element with a four-bit input in the live circuit embedded below:
+
+
+
+## Least Significant Bit (LSB) Detector
+
+The **Least Significant Bit (LSB)** detector circuit element outputs the bit position of the least significant bit of the input. In other words, it outputs the bit position of the leftmost bit. An enable output is also provided to show if the LSB detector is active. The bit position of the LSB is also shown in decimal form within the body of the LSB detector.
+
+You can verify the behavior of the **Least Significant Bit (LSB)** detector circuit element with a four-bit input in the live circuit embedded below:
+
+
+
+## Priority Encoder
+
+The **Priority Encoder** circuit element works similarly to the **MSB and LSB** detectors. There is a specific output based on the bit position of the MSB, irrespective of the lesser significant bits. An enable input is also provided to activate/deactivate the priority encoder. If there are N outputs, there will be 2^N inputs.
+
+In the live circuit embedded below, a **Priority Encoder** with four single-bit inputs (T3, T2, T1, and T0 from most to least-significant bit) and two single-bit outputs (O2 and O1 from most to least-significant bit). Table 4.6 displays the truth table of the four-input priority encoder.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth**
+
+Table 4.6: Truth table of a four-input priority encoder
+
+
+
+ T3 T2 T1 T0 O2 O1
+
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+
+
+ 0
+ 0
+ 1
+ X
+ 0
+ 1
+
+
+ 0
+ 1
+ X
+ X
+ 1
+ 0
+
+
+ 1
+ X
+ X
+ X
+ 1
+ 1
+
+
+
+
+
+## Decoder
+
+The **Decoder** circuit element includes N input bits and has 2^N output lines.
+
+In the live circuit embedded below, a **Decoder** with a single two-bit input (T1 and T0 from most to least-significant bit) and four single-bit output lines (O4, O3, O2, and O1 from most to least-significant bit). For the input values set in T1 and T0, the corresponding output line (O4, O3, O2, and O1) is HIGH. Table 4.7 displays the truth table for a two-bit decoder.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth**
+
+Table 4.7: Truth table of a two-bit decoder
+
+
+
+ T1 T0 O4 O3 O2 O1
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+
+
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+
+
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+
+
+
+
+## Parity Generator & Parity Detector
+
+The **Parity Generator** and **Parity Detector** combinational circuit elements are used together for error-tolerant data transmission. The **Parity Generator** circuit element is used by the sender, and the **Parity Detector** circuit element is used by the receiver.
+
+### Parity Generator
+
+The **Parity Generator** circuit element generates a parity bit which is later used by parity detectors to detect errors in data transmission. The parity bit is added to the original message that must be sent.
+
+If the input message of an even parity generator has an even number of `1`s, the parity bit will be 0. On the other hand, if there are an odd number of `1`s, the parity bit generated will be 1. Table 4.8 displays the truth table for an even three-bit input parity generator.
+
+Table 4.8: Truth table for an even three-bit parity generator
+
+
+
+ A B C PARITY BIT (P)
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+ 1
+ 1
+
+
+ 0
+ 1
+ 0
+ 1
+
+
+ 0
+ 1
+ 1
+ 0
+
+
+ 1
+ 0
+ 0
+ 1
+
+
+ 1
+ 0
+ 1
+ 0
+
+
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+
+
+
+If the input message of an odd parity generator has an even number of `1`s, the parity bit will be 1. Alternatively, if there are an odd number of `1`s, the parity bit generated will be 0. The parity bit generated is then added to the message to be sent. Table 4.9 displays the truth table for an odd three-bit input parity generator.
+
+Table 4.9: Truth table for an odd three-bit parity generator
+
+
+
+ A B C PARITY BIT (P)
+
+ 0
+ 0
+ 0
+ 1
+
+
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 1
+ 0
+ 0
+
+
+ 0
+ 1
+ 1
+ 1
+
+
+ 1
+ 0
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+ 1
+
+
+ 1
+ 1
+ 0
+ 1
+
+
+ 1
+ 1
+ 1
+ 0
+
+
+
+### Parity Detector
+
+The **Parity Detector** circuit element receives the message and checks it for errors. If an error is detected, the parity error check bit gives `1` as output and `0` when no error is detected. Table 4.10 and Table 4.11 display the truth tables for an even and odd three-bit input parity detector, respectively.
+
+
+
+ A B C P PARITY ERROR CHECK
+
+ 0 0 0 1 1
+
+
+ 0 0 1 0 1
+
+
+ 0 0 1 1 0
+
+
+ 0 1 0 0 1
+
+
+ 0 1 0 1 0
+
+
+ 0 1 1 0 0
+
+
+ 0 1 1 1 1
+
+
+ 1 0 0 0 1
+
+
+ 1 0 0 1 0
+
+
+ 1 0 1 0 0
+
+
+ 1 0 1 1 1
+
+
+ 1 1 0 0 0
+
+
+ 1 1 0 1 1
+
+
+ 1 1 1 0 1
+
+
+ 1 1 1 1 0
+
+
+
+
+
+ A B C P PARITY ERROR CHECK
+
+ 0 0 0 0 1
+
+
+ 0 0 0 1 0
+
+
+ 0 0 1 0 0
+
+
+ 0 0 1 1 1
+
+
+ 0 1 0 0 0
+
+
+ 0 1 0 1 1
+
+
+ 0 1 1 0 1
+
+
+ 0 1 1 1 0
+
+
+ 1 0 0 0 0
+
+
+ 1 0 0 1 1
+
+
+ 1 0 1 0 1
+
+
+ 1 0 1 1 0
+
+
+ 1 1 0 0 1
+
+
+ 1 1 0 1 0
+
+
+ 1 1 1 0 0
+
+
+ 1 1 1 1 1
+
+
+
+Although the parity detector can detect most errors, some of its limitations include:
+
+- Error is detected only if there are an odd number of error bits.
+- Error in parity bit might lead to error detection despite correct transmission.
+- Parity detector will not be able to detect errors where both parity and data bits have such an error that matches the parity bit.
+
+You can verify the same in the live circuit embedded below:
+
+
\ No newline at end of file
diff --git a/CircuitVerse-Documentation/docs/chapter4/6sequentialelements.mdx b/CircuitVerse-Documentation/docs/chapter4/6sequentialelements.mdx
new file mode 100644
index 00000000..f7ac8406
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter4/6sequentialelements.mdx
@@ -0,0 +1,588 @@
+---
+id: chapter4-sequentialelements
+title: "Sequentialelements"
+description: "Sequentialelements page in Chapter4 of CircuitVerse documentation."
+---
+
+# Sequential Elements
+
+CircuitVerse features the following circuit elements in this category:
+
+- [Sequential Elements](#sequential-elements)
+ - [D Flip Flop](#d-flip-flop)
+ - [D Latch](#d-latch)
+ - [T Flip Flop](#t-flip-flop)
+ - [SR Flip Flop](#sr-flip-flop)
+ - [JK Flip Flop](#jk-flip-flop)
+ - [TTY](#tty)
+ - [Keyboard](#keyboard)
+ - [Clock](#clock)
+ - [ROM](#rom)
+ - [RAM](#ram)
+ - [EEPROM](#eeprom)
+
+## D Flip Flop
+
+A delay or D Flip Flop circuit element delays the input. As Figure 4.3 shows, it takes in a single data input and a clock input. Some of the other pins include:
+
+1. Preset and Asynchronous Reset: The preset and asynchronous reset pins work in conjunction to change the default behavior of the flip flops.
+
+ Figure 4.3: Pin description of the D Flip Flop within the CircuitVerse
+ platform
+
+
+
+Table 4.12: Table for D Flip Flop circuit element
+
+
+
+ Clock
+ D
+ Q
+ Q Inverse
+
+
+ 0
+ X
+ Latch
+ Latch
+
+
+ 1
+ 1
+ 1
+ 0
+
+
+ 1
+ 0
+ 0
+ 1
+
+
+
+You can verify the behavior of the D Flip Flop circuit element in the live circuit embedded below:
+
+
+
+## D Latch
+
+The **D Latch** circuit element is a single input flip flop. As Figure 4.4, it works similar to a **D Flip Flop** but it does not include the preset, asynchronous and enable signal pins. The truth table of a D Latch (refer Table 4.13) is similar to that of the D Flip Flop.
+
+> Properties that can be customized in the **PROPERTIES** panel include:\*\* **BitWidth**
+
+
+
+
+
+ Figure 4.4: Pin description of the D Latch within the CircuitVerse platform
+
+
+
+Table 4.13: Table for D Latch circuit element
+
+
+
+
+ Clock
+
+
+ D
+
+
+ Q
+
+
+ Q Inverse
+
+
+
+ 0
+ X
+ Latch
+ Latch
+
+
+ 1
+ 1
+ 1
+ 0
+
+
+ 1
+ 0
+ 0
+ 1
+
+
+
+/* You can verify the behavior of the **D Latch** circuit element in the live circuit embedded below:
+[insert live cirucit] */
+
+## T Flip Flop
+
+A toggle or **T Flip Flop** circuit element toggles the output. As Figure 4.5 shows, it takes in a single data input and a clock input. As Table 4.14 (the truth table for T Flip Flop) displays, if the value of the input is 1, then the output of the next state is the complement of the previous state.
+
+
+
+
+
+ Figure 4.5: Pin description of the T Flip Flop within the CircuitVerse
+ platform
+
+
+
+Table 4.14: Table for T Flip Flop circuit element
+
+
+
+
+ Input (T)
+
+
+ Previous State
+
+
+ Next State
+
+
+
+ 0
+ 0
+ 0
+
+
+ 0
+ 1
+ 1
+
+
+ 1
+ 0
+ 1
+
+
+ 1
+ 1
+ 0
+
+
+
+You can verify the behavior of the **T Flip Flop **circuit element in the live circuit embedded below:
+
+
+
+## SR Flip Flop
+
+A **SR Flip Flop** circuit element is one of the simplest sequential circuits. It has two inputs S (stands for “Set”) and R (stands for “Reset”) along with the clock (refer Figure 4.6). As Table 4.15 (the truth table for SR Flip Flop) demonstrates:
+
+- When S is HIGH, the output Q is HIGH.
+- When R is HIGH, the output is LOW.
+
+
+
+
+
+ Figure 4.6: Pin description of the SR Flip Flop within the CircuitVerse
+ platform
+
+
+
+Table 4.15: Table for SR Flip Flop circuit element
+
+
+
+
+ S
+
+
+ R
+
+
+ Q
+
+
+
+ 0
+ 0
+ No change
+
+
+ 1
+ 0
+ 1
+
+
+ 0
+ 1
+ 0
+
+
+ 1
+ 1
+ Invalid
+
+
+
+You can verify the behavior of the **SR Flip Flop** circuit element in the live circuit embedded below:
+
+
+
+## JK Flip Flop
+
+The **JK Flip Flop** circuit element, an improvement of a SR Flip Flop, includes two inputs J and K along with the clock (refer Figure 4.7). As Table 4.16 (the truth table for a JK flip flop) explains, if the inputs J and K are different, then the output Q takes the value of the input J at the next clock edge.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth**
+
+
+
+
+
+ Figure 4.7: Pin description of the JK Flip Flop within the CircuitVerse
+ platform
+
+
+
+Table 4.16: Table for JK Flip Flop circuit element
+
+
+
+
+ J
+
+
+ K
+
+
+ Q
+
+
+
+ 0
+ 0
+ No change
+
+
+ 1
+ 0
+ 1
+
+
+ 0
+ 1
+ 0
+
+
+ 1
+ 1
+ Toggle
+
+
+
+You can verify the behavior of the JK Flip Flop circuit element in the live circuit embedded below:
+
+
+
+## TTY
+
+A **TTY** circuit element receives an input sequence of ASCII codes and displays each printable character as output. While Figure 4.8 displays the different pins of TTY, Table 4.17 gives a brief description of the different pins.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth must be set as 7, Rows, Columns**
+
+
+
+
+
+ Figure 4.8: Pin description of the TTY circuit element within the
+ CircuitVerse platform
+
+
+
+Table 4.17: Pin description of TTY circuit element within CircuitVerse simulator
+
+
+
+ Name
+ Description
+
+
+ ASCII Input (BitWidth 7)
+ Receives the ASCII value of the next character to be entered into the terminal.
+
+
+ Clock (BitWidth 1)
+ When the clock is triggered and the Enable pin isn't 0, the current ASCII input is processed by the terminal.
+
+
+ Enable (BitWidth 1)
+
+
+
+When the Enable pin is 1, a clock edge will result in processing a new character from the data input.
+
+When the Enable pin is 0, the clock and data inputs are ignored.
+
+
+
+
+ Reset
+
+
+
+When the Reset pin is 1, the terminal is cleared of all data and the other inputs are ignored.
+
+
+
+
+
+You can verify the behavior of the TTY circuit element in the live circuit embedded below:
+
+
+
+## Keyboard
+
+The **Keyboard** circuit element allows the circuit to read keystrokes, as long as the keystrokes are representable in the seven-bit ASCII code. Figure 4.9 shares the pin description of the **Keyboard** circuit element and Table 4.18 shares a brief description of the same.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Buffer Size**
+
+
+
+
+
+ Figure 4.9: Pin description of the Keyboard circuit element within the
+ CircuitVerse platform
+
+
+
+Table 4.18: Pin description of Keyboard circuit element within CircuitVerse simulator
+
+
+
+ Name
+ Description
+
+
+ Clock (BitWidth 1)
+ When the clock is triggered and the Enable pin isn't 0, the leftmost character from the buffer is deleted and the outputs are updated to reflect the buffer's new status.
+
+
+ Enable (BitWidth 1)
+
+
+When the Enable pin is 1, a clock edge will result in processing a new character from the data input.
+
+When the Enable pin is 0, the clock and data inputs are ignored.
+
+
+
+
+ Reset
+
+
+
+When the Reset pin is 1, the terminal is cleared of all data and does not accept any further characters
+
+
+
+
+ Available (AVL)
+
+
+
+Set as 1 when the buffer contains at least one character.
+
+Set as 0 when the buffer is empty.
+
+
+
+
+ ASCII Output (BitWidth 7)
+ Generates the 7-bit ASCII code for the leftmost character in the buffer or 0 if the buffer is empty.
+
+
+
+You can verify the behavior of the **Keyboard** circuit element in the live circuit embedded below:
+
+
+
+## Clock
+
+The **Clock **circuit element toggles its output at regular time intervals.
+
+> NOTE: All clocks enabled within a circuit toggle at the same rate.
+
+You can verify the behavior of the **Clock** circuit element in the live circuit embedded below:
+
+## ROM
+
+As the name suggests, the **ROM **( read-only memory) circuit element stores read only data for computers and other electronic devices. ROM is mostly used for firmware updates. A simple example of ROM is the cartridge used with video game consoles, which allows one system to run multiple games. Another example of ROM is EEPROM, which is a programmable ROM used for the computer BIOS.
+
+The **ROM** circuit element includes three pins. As Figure 4.10 elucidates, it accepts a 4-bit address input (**A**) and the corresponding value stored in the particular address is returned as a 8-bit output (**D**) (initial address always starts from 0). The Enable (**En**) pin enables the ROM.
+
+
+
+
+ Figure 4.10: ROM circuit element within the CircuitVerse platform
+
+
+You can verify the behavior of the **ROM** circuit element in the live circuit embedded below:
+
+
+
+## RAM
+
+The **RAM** ( random access memory) circuit element allows data to be read or written. Any changes to **Address Width** property attribute and **BitWidth** property attribute will cause data to be lost (refer Figure 4.11). Think of these operations as being equivalent to taking a piece of RAM out of a circuit board and replacing it with another RAM of different size.
+
+Data stored within the RAM can be reset to zero by setting the Reset pin 1 or clicking the **Reset** button in the **PROPERTIES** panel. Refer Figure X.
+
+Alternatively, the contents of the RAM can be dumped to the console by transitioning the **Core Dump** pin to 1 or clicking the **Core Dump** button in the **PROPERTIES** panel. Any address spaces that have not been written will show up as undefined in the core dump.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Address Width, BitWidth**
+
+
+
+
+
+ Figure 4.11: RAM circuit element and relevant property attributes available
+ in the PROPERTIES panel
+
+
+
+You can verify the behavior of the **RAM **circuit element in the live circuit embedded below:
+
+
+
+## EEPROM
+
+The **EEPROM** circuit element is a programmable ROM used for the computer BIOS. EEPROMs are generally more expensive than RAMs. The maximum address space of the **EEPROM** circuit element is 10-bits (1024 addresses)––smaller than the RAM. Figure 4.12 shares a pin description of the **EEPROM **circuit element.
+
+
+
+
+
+ Figure 4.12: EEPROM circuit element available within the CircuitVerse
+ simulator
+
+
+
+If the EEPROM is erased, all the values are reset to zero and the original data cannot be recovered. The project can be reloaded for retrieving the saved data.
+
+EEPROM data survives cut-and-paste operations and can be used for different purposes like duplicating EEPROMs, creating an EEPROM in one circuit and then cut-and-pasting the element in another circuit,or create a library of ready-to-use EEPROMs with interesting data.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Address Width, BitWidth**
+
+You can verify the behavior of the EEPROM circuit element in the live circuit embedded below:
+
+1. To populate the EEPROM, make **Write**=1 and click **Reset** to erase everything.
+2. Click the **Keyboard** circuit element and type some characters until the address counter in the EEPROM goes back to zero.
+3. Make **Write**=0 and the text in the EEPROM will show in the TTY element.
+4. Save the circuit and it will persist the contents of the EEPROM for future use
+
+
diff --git a/CircuitVerse-Documentation/docs/chapter4/7annotation.mdx b/CircuitVerse-Documentation/docs/chapter4/7annotation.mdx
new file mode 100644
index 00000000..cead6445
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter4/7annotation.mdx
@@ -0,0 +1,72 @@
+---
+id: chapter4-annotation
+title: "Annotation"
+description: "Annotation page in Chapter4 of CircuitVerse documentation."
+---
+
+# Annotation
+
+This section highlights the different annotation elements available in the **CIRCUIT ELEMENTS** panel for circuit description. A circuit schematic can be annotated by:
+
+- Adding labels across different nodes.
+- Including text boxes for displaying relevant project information such as the version number, date, group members involved, etc..
+- Adding rectangular boxes for highlighting different sections for complex designs.
+- Inserting images for sharing more information about the project.
+
+Additionally, most of the circuit elements listed in the **CIRCUIT ELEMENTS** panel can be individually described on the **Canvas** using the **Label** and **Label Direction** attributes available in the **PROPERTIES** panel (refer Figure 4.13).
+
+
+
+
+
+ Figure 4.13: Add labels for individually describing the relevant circuit
+ element on the Canvas
+
+
+
+## Rectangle
+
+The **Rectangle** annotation element allows the user to draw attention to a specific portion of the circuit. Refer Figure 4.14 for how a user has the **Rectangle** circuit element for highlighting the key portion of the circuit.
+
+**Properties that can be customized in the PROPERTIES panel include:** **Rows, Columns**
+
+
+
+
+
+ Figure 4.14: Live circuit annotation using different annotation elements
+ available within CircuitVerse
+
+
+
+## Arrow
+
+Similar to the **Rectangle** annotation element, the **Arrow** annotation element (refer Figure 4.14) allows the user to draw attention to a specific portion of the circuit. The direction of the **Arrow** circuit element can be changed either by using the arrow keys on your keyboard or using the **PROPERTIES** panel to edit the **Direction**: attribute (refer Figure 4.15).
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Direction**
+
+
+
+
+ Figure 4.15: Relevant attributes for the Arrow annotation element
+
+
+## ImageAnnotation
+
+The **ImageAnnotation** annotation element allows the user to upload images inside the live circuit. As needed, the height and width of the uploaded image can be changed by editing the **Rows** and **Columns** attributes available for the **ImageAnnotation** annotation element in the **PROPERTIES** panel (refer Figure 4.16).
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Rows, Columns**
+
+
+
+
+
+ Figure 4.16: Relevant attributes for the ImageAnnotation annotation element
+
+
+
+## Text
+
+The **Text** annotation element allows users to add multi-line text to share more information about the live circuit––circuit logic design details of the circuit, expected behavior of the circuit, etc.. Refer Figure 4.14.
+
+> Properties that can be customized in the **PROPERTIES** panel include:\*\* **Font size**
diff --git a/CircuitVerse-Documentation/docs/chapter4/8misc.mdx b/CircuitVerse-Documentation/docs/chapter4/8misc.mdx
new file mode 100644
index 00000000..ee8f0d61
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter4/8misc.mdx
@@ -0,0 +1,521 @@
+---
+id: chapter4-misc
+title: "Misc"
+description: "Misc page in Chapter4 of CircuitVerse documentation."
+---
+
+# Misc
+
+1. [ALU](#alu)
+2. [Adder](#adder)
+3. [Buffer](#buffer)
+4. [TriState Buffer](#tristate-buffer)
+5. [Tunnel](#tunnel)
+6. [Splitter](#splitter)
+7. [Equal Split](#equal-split)
+8. [Unequal Split](#unequal-split)
+9. [Flag](#flag)
+10. [Two's Complement](#twos-complement)
+
+## ALU
+
+An **Arithmetic Logic Unit** (ALU) circuit element is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. Figure 4.15 highlights the different ports in the ALU circuit element available within CircutVerse and Table 4.19 provides a brief description of the different ports.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Direction, BitWidth**
+
+Table 4.19: Brief description of the ALU circuit element ports
+
+
+
+ Name
+ Description
+
+
+ A
+ Receives an input operand
+
+
+ B
+ Receives an input operand.
+
+
+ CTR (BitWidth 3)
+ Receives an input operand with bit width of 3 bits.
+
+
+ Ans
+
+ Generates the output after the operation on the received input operands
+ has been completed.
+
+
+
+ Carry
+
+ Generates the carry output after the operation on the received input
+ operands has been completed.
+
+
+
+
+
+
+
+ Figure 4.17: Relevant attributes for the ALU circuit element
+
+
+As required, the users may change the orientation of the ALU circuit element by editing the **Direction** attribute available for the **ALU** circuit element in the **PROPERTIES** panel (refer Figure 4.17). Alternatively, users can use the arrow keys on their keyboard to change the orientation.
+
+In the embedded circuit below, A and B are two operands.Table 4.20 displays the opcodes for different ALU functionalities.
+
+> Note: SLT (Set Less Than): If A is less than B, output is 1 else output is 0.
+
+Table 4.20: CTR port input opcodes for different functionalities of ALU
+
+
+
+
+ Opcode
+
+
+ Opcode Value
+
+
+ Operation
+
+
+
+ 0 0 0
+ 0
+ A & B
+
+
+ 0 0 1
+ 1
+ A | B
+
+
+ 0 1 0
+ 2
+ A + B
+
+
+ 1 0 0
+ 4
+ A & ~B
+
+
+ 1 0 1
+ 5
+ A | ~B
+
+
+ 1 1 0
+ 6
+ A - B
+
+
+ 1 1 1
+ 7
+ SLT
+
+
+
+
+
+## Adder
+
+The **Adder** circuit element is a logical circuit of a full adder that performs an addition operation on binary numbers and produces a sum of the three inputs and a carry value (Cout). Figure 4.18 displays the different pins available for the **Adder **circuit element within CircuitVerse and Table 4.21 shares a brief description of the same.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Direction**
+
+
+
+
+
+ Figure 4.18: Pin description of the Adder circuit element within the
+ CircuitVerse platform
+
+
+
+Table 4.21: Brief description of the **Adder** circuit element
+
+
+
+ Name
+ Description
+
+
+ A
+ Receives an input operand
+
+
+ B
+ Receives an input operand.
+
+
+ Cin
+ Receives an input carry value operand
+
+
+ Sum
+
+ Generates the output after the operation on the received input operands.
+ ((A XOR B) XOR Cin)
+
+
+
+ Cout
+
+ Generates the carry left over after the output operation has been
+ completed. ((A AND B) OR (Cin AND (A XOR B) )
+
+
+
+
+Using Table 4.22, you can verify the behavior of the **Adder** circuit element in the live circuit embedded below:
+
+Table 4.22: Truth Table for an adder
+
+
+
+
+ A
+
+
+ B
+
+
+ Cin
+
+
+ SUM
+
+
+ Cout
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+ 1
+ 1
+ 0
+
+
+ 0
+ 1
+ 0
+ 1
+ 0
+
+
+ 0
+ 1
+ 1
+ 0
+ 1
+
+
+ 1
+ 0
+ 0
+ 1
+ 0
+
+
+ 1
+ 0
+ 1
+ 0
+ 1
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+
+
+
+
+
+## Buffer
+
+The **Buffer** circuit element has only a single input and a single output. Its behavior is the opposite of a NOT gate––passes its input unchanged to its output. Table 4.23 displays the truth table of a buffer.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Direction**
+
+Table 4.23: Truth table for a buffer
+
+
+
+ Input
+ Output
+
+
+ 0
+ 0
+
+
+ 1
+ 1
+
+
+
+You can verify the behavior of the **Buffer** circuit element in the live circuit embedded below:
+
+
+
+## TriState Buffer
+
+The **TriState** buffer circuit element behaves similar to a buffer. As Figure 4.17 illustrates, this circuit element includes an additional **Enable** input that controls whether the primary input is passed to its output or not.
+
+- If the **Enable** input signal is HIGH, the tri-state buffer behaves like a normal buffer.
+- If the **Enable** input signal is LOW, the tri-state buffer passes a high impedance signal which effectively disconnects its output from the circuit.
+
+If required, a user can change the orientation of the circuit element using the arrow keys on the keyboard or editing the value of the **Direction** attribute available in the **PROPERTIES** panel for the **TriState** buffer circuit element.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Direction, BitWidth**
+
+
+
+
+ Figure 4.19: Relevant attributes for the TriState circuit element
+
+
+Table 4.24: Truth table for a TriState buffer
+
+
+
+
+ Enable
+
+
+ Input
+
+
+ Output
+
+
+
+ 0
+ 0
+ Z
+
+
+ 0
+ 1
+ Z
+
+
+ 1
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+
+
+
+You can verify the behavior of the **TriState** buffer circuit element in the live circuit embedded below:
+
+
+
+## Tunnel
+
+The **Tunnel** circuit element encapsulates desired connection points in a tunnel for transmitting signals without using a wire (refer Figure 4.18). It is recommended to use this circuit element for design areas that may require excessive wiring to connect otherwise.
+
+
+
+
+
+ Figure 4.20: Relevant property attributes for the Tunnel circuit element
+
+
+
+When the **Tunnel** circuit element is implemented in a circuit design, tunnels with the same **Debug Flag identifier** attribute (available in the **PROPERTIES** panel for the **Tunnel** circuit element(refer Figure 4.18)) are connected together.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **BitWidth, Direction, Debug Flag identifier**
+
+You can verify the behavior of the **Tunnel** circuit element in the live circuit embedded below:
+
+
+
+## Splitter
+
+Splitters split high bitwidth wires (buses) into lower bitwidth wires(buses) and vice versa. It is the only two-way circuit element in CircuitVerse.
+
+The bitwidth may be split into equal parts or unequal parts. Consider that you have a 4 bitwith bus. You may split it into equal or unequal parts as shown below:
+
+- Equal parts: 4 -> 1 1 1 1
+- Unequal parts: 4 -> 1 2 1
+
+Figure 4.21 shows the relevant properties for a 4 bitwidth splitter split into equal parts.
+
+> Properties that can be customized in the **PROPERTIES** panel include: **Direction**
+
+
+
+
+ Figure 4.21: Relevant properties for the Splitter circuit element
+
+
+When the **Splitter** circuit element is dragged on the **Canvas**, the bitwidth window pops up (refer Figure 4.22) where the user must first identify the total bits the bus.
+
+
+
+
+ Figure 4.22: Splitter bitwidth window
+
+
+In the follow up window, the user can then identify if the bitwidth must be split into equal or unequal parts.
+
+
+
+
+ Figure 4.23: Splitter bitwidth split window
+
+
+### Equal Split
+
+You can verify the behavior of the **Splitter** circuit element when the bitwidth is split in equal parts in the live circuit embedded below:
+
+
+
+### Unequal Split
+
+You can verify the behavior of the **Splitter** circuit element when the bitwidth is split in unequal parts in the live circuit embedded below:
+
+
+
+## Flag
+
+The **Flag** circuit element is used in a circuit design to flag outputs at different points in your circuit. Figure X highlights the different attributes that are available for this circuit element.
+
+> Properties that can be customized in the **PROPERTIES** panel include**: **BitWidth, Orientation, Debug Flag identifier\*\*
+
+
+
+
+ Figure 4.24: Relevant attributes for the Flag circuit element
+
+
+## Two's Complement
+
+The **Two’s Complement** circuit element calculates the two’s complement of any binary number. A two's complement operation is simply a one's complement operation followed by the addition of 1 to the result.
+
+```
+Given number 1 1 1 1 0
+1's complement 0 0 0 0 1
+add 1 + 1
+ ---------------
+2's complement 0 0 0 1 0
+```
+
+You can verify the behavior of the **Two’s Complement** circuit element in the live circuit embedded below:
+
+
diff --git a/CircuitVerse-Documentation/docs/chapter5/usingeditlayout.mdx b/CircuitVerse-Documentation/docs/chapter5/usingeditlayout.mdx
new file mode 100644
index 00000000..c40e9838
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter5/usingeditlayout.mdx
@@ -0,0 +1,66 @@
+---
+id: chapter5-usingeditlayout
+title: "Usingeditlayout"
+description: "Usingeditlayout page in Chapter5 of CircuitVerse documentation."
+---
+
+# Using Edit Layout
+
+After a subcircuit has been successfully populated, the circuit layout can be edited using the **Edit Circuit Layout** setting available on the **Properties Panel**. The **Edit Circuit Layout** setting generates the circuit layout (with valid input and output connections) as a black box. The circuit elements and the relevant connections are hidden whereas the input and output pins are displayed. This clean design schematic adds more clarity and reduces the cognitive load on the user.
+
+As required, a user can use the **LAYOUT ELEMENTS** panel to add any circuit elements inside the black box (to observe the behavior of the circuit when the circuit) , and the **LAYOUT** panel to improve the layout of the circuit. Refer Figure 5.3. Table 5.1 provides a brief description of the different settings available on the **LAYOUT** panel.
+
+> NOTE: Circuit layout must be edited before inserting a circuit or completing the wiring connections. If the node positions within the circuit layout are edited after making the wiring connections, then some of the wiring connections across different nodes or ports in the integrated circuit schematic may be lost.
+>
+> TIP: Make all the necessary changes within the circuit layout prior to the wiring connections.
+
+
+
+
+ Figure 5.3
+
+
+Table 5.1: Brief description of the different settings available on the **LAYOUT** panel
+
+
+
+
+ Setting
+
+
+ Description
+
+
+
+ Width
+
+ Displays a numeric stepper to manage the width of the circuit layout.
+
+
+
+ Height
+
+ Displays a numeric stepper to manage the height of the circuit layout.
+
+
+
+ Reset all nodes
+ Resets the nodes to their default position.
+
+
+ Title Enabled
+
+ Displays or hides the title of the subcircuit. By default, the title is
+ displayed for each circuit layout.
+
+
+
+ Title Position
+
+ Positions the title at a desired location using the up, down, right and
+ left arrows.
+
+
+
+
+To learn more about how to use subcircuits and Edit Layout for building circuits, refer [Chapter 7](/chapter7/2buildwithcv.mdx).
diff --git a/CircuitVerse-Documentation/docs/chapter5/usingsubcircuits.mdx b/CircuitVerse-Documentation/docs/chapter5/usingsubcircuits.mdx
new file mode 100644
index 00000000..a885eeaa
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter5/usingsubcircuits.mdx
@@ -0,0 +1,30 @@
+---
+id: chapter5-usingsubcircuits
+title: "Usingsubcircuits"
+description: "Usingsubcircuits page in Chapter5 of CircuitVerse documentation."
+---
+
+# Using Subcircuits
+
+As digital circuit designs grow in size and complexity, capturing a large, abstract design at the gate level can become complex, prone to error and require more time for development, synthesis, simulation and debugging.
+
+For a hierarchical design flow, different circuit tabs can be inserted as a subcircuit inside another circuit tab. A subcircuit is a modular functional block that delivers a single function within a given design. This makes the design modular and easy to troubleshoot. As Figure 5.1 elucidates, any changes to the circuit layout must be done before inserting a circuit and making the wire connections. If the node positions within the circuit layout are edited after making the wiring connections, then some of the wiring connections across different nodes or ports in the integrated circuit schematic may be lost.
+
+
+
+
+
+ Figure 5.1: Ideal circuit design flow for for an integrated effort while
+ using subcircuits within CircuitVerse
+
+
+
+## Insert Verilog Modules as Subcircuits
+
+Besides inserting CircuitVerse generated circuit designs, Verilog modules can also be inserted as subcircuits. Users can enter the code in the module interface and save the code to generate the circuit layout (refer Figure 5.2). Unlike CircuitVerse simulations, the circuit generated using a Verilog module cannot be simulated.
+
+
+
+
+ Figure 5.2: Add Verilog code to generate the circuit layout
+
diff --git a/CircuitVerse-Documentation/docs/chapter6/delayvsclock.mdx b/CircuitVerse-Documentation/docs/chapter6/delayvsclock.mdx
new file mode 100644
index 00000000..643cb337
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter6/delayvsclock.mdx
@@ -0,0 +1,37 @@
+---
+id: chapter6-delayvsclock
+title: "Delayvsclock"
+description: "Delayvsclock page in Chapter6 of CircuitVerse documentation."
+---
+
+# Clock Time versus Delay
+
+Before exploring how to visualize a timing diagram for a given circuit, this section explores some key concepts that define the working of the **TIMING DIAGRAM** panel.
+
+## Clock Time (ms):
+
+The **Clock Time** property attribute in Figure 6.1 refers to the time interval for the half cycle of a circuit. Changing the clock time interval speeds up or slows down the circuit simulation. However, it should be noted that changing the **Delay** attribute for any circuit element doesn't change circuit behavior. This clock frequency is only for demonstration purposes.
+
+
+
+
+
+ Figure 6.1: The Clock Time(ms) property attribute is the time interval for
+ the half cycle of a circuit{" "}
+
+
+
+## Delay
+
+The **Delay** property parameter for a circuit element delays refers to propagation delays. It should be noted that the delays are simulated––they are virtual and therefore not rendered.
+
+The **Delay** parameter doesn't have a unit as delays are processed relative to each other. Unlike the **Clock Time (ms)** attribute, the **Delay** parameter changes the behaviour of the circuit and should be used to resolve race conditions. They can be visualized using a timing diagram as described in the next section.
+
+## Clock Time and Delay: CircuitVerse Implemented Restrictions
+
+The below design restrictions have been implemented in the CV simulator to ease the design and verification of circuits, without imposing untoward restrictions:
+
+1. Real life circuits go into a stable state between clock ticks. Irrespective of any implemented circuit element delays, the circuits go into a stable state between clock ticks. The CV simulator thus cannot simulate circuits that do not go into a stable state between clock ticks.
+2. Similarly, circuits go into a stable state before processing input signals from different input elements like buttons and stepper.
+3. Contamination delay = Propagation delay
+4. Hold time = 0
diff --git a/CircuitVerse-Documentation/docs/chapter6/timingdiagram.mdx b/CircuitVerse-Documentation/docs/chapter6/timingdiagram.mdx
new file mode 100644
index 00000000..628517ba
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter6/timingdiagram.mdx
@@ -0,0 +1,55 @@
+---
+id: chapter6-timingdiagram
+title: "Timingdiagram"
+description: "Timingdiagram page in Chapter6 of CircuitVerse documentation."
+---
+
+# Timing Diagram
+
+A timing diagram is used for analyzing and debugging the behavior of circuits for different input sequences. Using the **Flag** circuit element, timing diagrams can be used to debug logical mistakes and race conditions. Additionally, this can be used to explain different concepts such as propagation delay, stable state and race conditions.
+
+> Note: The timing diagram may not be accurate if used with both clock and user input. Ideally the circuit should be driven completely by the clock or completely driven by user input.
+
+Similar to other panels available in the CV simulator, the **TIMING DIAGRAM** panel is collapsible and can be dragged by the mouse. Figure 6.2 elucidates the different icons available on the **TIMING DIAGRAM** panel for plotting a waveform.
+
+
+
+
+
+ Figure 6.2: Description of different icons available on the Timing Diagram
+ panel{" "}
+
+
+
+## Mapping Delays While Using Timing Diagram
+
+In order to visualize a timing diagram, it is necessary to map the simulation delay units in a single half clock cycle. This is done by setting “**1 cycle = \_\_\_ units”** (Refer Figure 6.2. Icon description of number 8). While this number can be set auto calibrated by clicking on the **Auto Calibrate** icon in the **TIMING DIAGRAM** panel, this number must exceed the delay in the critical path of the circuit.
+
+Similarly, the clock interval maps how many milliseconds are there in one half clock cycle. As explained below, the delays can also be indirectly mapped to time.
+
+- 1 clock cycle --> 500 ms
+- 1 clock cycle --> 50 units
+- 1 unit --> 10 ms
+
+## Understanding Circuit Behavior Using Timing Diagram
+
+Figure 6.3 illustrates a circuit design where two NOT gates cancel out each other to behave as an XNOR gate.
+
+
+
+
+ Figure 6.3
+
+
+**Reading **TIMING DIAGRAM** panel**: The delay has been set to 1 clock cycle = 50 units. So each unit is 2% of a clock cycle. Therefore, 10 units is 20% of a clock cycle.
+
+- 1 clock cycle --> 500 ms
+- 1 clock cycle --> 50 units
+- 1 unit --> 10 ms
+
+**Visualizing circuit behavior using the **TIMING DIAGRAM** panel**: The two NOT gates cancel out each other to behave as an XNOR gate. Thus, irrespective of the input set, the output must be 1. However, the **TIMING DIAGRAM** panel shows that after 10 units of time, flag **F1** moves from 0 -->1. After an additional 10 units of time, flag **F2** goes to 0. This happens because the first input of XNOR gate becomes 1 but the second input is still 0 (due to NOT gate delays). After an additional 20 units of NOT gate delay, the circuit becomes stable and flag **F2** goes back to 1.
+
+1. Time = 0 | F1 = 0, F2 = 1 (stable state)
+2. Time = 10 | F1 = 1, F2 = 1 (unstable state)
+3. Time = 20 | F1 = 1, F2 = 0 (unstable state - glitch) (XNOR delay)
+4. Time = 40 | F1 = 1, F2 = 1 (stable state) (2 NOT gates + XNOR delay)
diff --git a/CircuitVerse-Documentation/docs/chapter7/1cvdesignprocess.mdx b/CircuitVerse-Documentation/docs/chapter7/1cvdesignprocess.mdx
new file mode 100644
index 00000000..afdf353f
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter7/1cvdesignprocess.mdx
@@ -0,0 +1,13 @@
+---
+id: chapter7-cvdesignprocess
+title: "Cvdesignprocess"
+description: "Cvdesignprocess page in Chapter7 of CircuitVerse documentation."
+---
+
+# Understanding CircuitVerse Design Process
+
+CircuitVerse simulator allows users to build and simulate their designs on the go. Users can build a circuit by dragging elements from the **CIRCUIT ELEMENTS** panel and setting the relevant properties for each element using the **PROPERTIES** panel. Different circuit elements can then be connected by clicking on the output of one gate or port, and dragging the mouse to the input of the next one. While nesting circuits within one another, the circuit layout must be edited before inserting the subcircuit. If required, the **Combinational Analysis** tool can also be used to simulate the behavior of a functional design using truth tables and Boolean expressions.
+
+Finally, the circuit schematic must be annotated using the different annotation elements available in the **PROPERTIES** panel. Any questions or suggestions can be shared with the CircuitVerse Forum where CircuitVerse mentors and a growing community of users can answer your queries or share quick workarounds.
+
+For best practices of building circuits within CircuitVerse, [refer this section](/chapter2/4bestpracticescv.mdx).
diff --git a/CircuitVerse-Documentation/docs/chapter7/2buildwithcv.mdx b/CircuitVerse-Documentation/docs/chapter7/2buildwithcv.mdx
new file mode 100644
index 00000000..702a2440
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter7/2buildwithcv.mdx
@@ -0,0 +1,262 @@
+---
+id: chapter7-buildwithcv
+title: "Buildwithcv"
+description: "Buildwithcv page in Chapter7 of CircuitVerse documentation."
+---
+
+# Building Circuit Simulations within CircuitVerse
+
+In this section, we will build a circuit of a full adder exploring the different stages of building a live circuit within the CircuitVerse simulator. We will start off by creating a circuit of a half adder and insert it as a subcircuit to create a 4-bit full adder.
+
+- [Building Circuit Simulations within CircuitVerse](#building-circuit-simulations-within-circuitverse)
+ - [Create and Save New Project](#create-and-save-new-project)
+ - [Create Circuit Using CircuitVerse Simulation](#create-circuit-using-circuitverse-simulation)
+ - [Edit Circuit Layout](#edit-circuit-layout)
+ - [Insert Subcircuit](#insert-subcircuit)
+ - [a. Insert Subcircuit as a CircuitVerse Simulation](#a-insert-subcircuit-as-a-circuitverse-simulation)
+ - [b. Insert Circuit Using Verilog Module](#b-insert-circuit-using-verilog-module)
+ - [Annotate Circuit](#annotate-circuit)
+
+## Create and Save New Project
+
+Although the CircuitVerse simulator saves the circuit periodically and any unsaved circuits may be recovered from the browsers memory, the user must create an account and save the CircuitVerse project online for future reference.
+
+Follow the below steps to create a new project and save the circuit online:
+
+1. Navigate to [https://circuitverse.org/](https://circuitverse.org/).
+
+2. Click on the **Launch Simulator** button to launch the simulator. Refer Figure 7.1.
+
+ 
+
+
+ Figure 7.1
+
+
+3. Navigate to the **Quick Access Panel**. Click on either **Save Online** icon or **Save Offline** icon to receive the** Enter Project Name**: pop-up window for saving the circuit. Refer Figure 7.2.
+
+ > NOTE: If a project file is saved online, it is available on the dashboard. Alternatively, any project file that is saved offline, is downloaded to your browser’s local storage.
+
+ 
+
+
+ Figure 7.2
+
+
+4. If the project is saved online, you will be directed to the **Edit Project** details page for sharing more information about the project (refer Figure 7.3).
+
+ 
+
+
+ Figure 7.3
+
+
+ Watch this video for more information on the different fields that can be used for sharing more information about the project.
+
+
+
+
+ .
+
+5. Click **Update Project** to save the project details and return back to the CV simulator window. Refer Figure 7.4.
+
+ 
+
+
+ Figure 7.4
+
+
+## Create Circuit Using CircuitVerse Simulation
+
+After successfully creating a CircuitVerse user account, follow the below steps for creating a circuit of a half adder within the CircuitVerse simulator:
+
+6. Navigate to the **CIRCUITS ELEMENTS** panel. Identify the relevant circuit elements and drop them on the canvas. If required, you may search for an element in the search bar. Refer Figure 7.5.
+
+ 
+
+
+ Figure 7.5
+
+
+7. Connect the circuit elements by clicking on one node and dragging the mouse to the other node. Refer to Figure 7.6 for the final circuit connection.
+
+ > TIP: Hold down Ctrl key. Click on a node and simply move the cursor to the final node to which it needs to be attached. Clicking on the wire will insert a node at that position. Upon reaching the final node, leave the Ctrl key and click on the node to end the wire.
+
+ 
+
+
+ Figure 7.6
+
+
+8. Select a circuit element. It will be highlighted in yellow as shown in Figure 7.7.
+
+9. Navigate to the **PROPERTIES** panel. Edit the **Label** parameter to add a label for the selected circuit element. Refer Figure 7.7.
+
+ 
+
+
+ Figure 7.7
+
+
+10. Repeat steps 3 and 4 to add labels for the remaining circuit elements as shown in Figure 7.7.
+
+## Edit Circuit Layout
+
+Before inserting a circuit as a subcircuit, the circuit layout must be edited to prevent any loss of wiring connections across different nodes or ports in the integrated circuit schematic may be lost.
+
+Follow the below steps to view and edit the circuit layout of the half-adder circuit:
+
+11. Navigate to the **PROPERTIES** panel.
+
+12. Click on the **Edit Layout** button to display the circuit layout for the built circuit (refer Figure 7.8).
+
+ 
+
+
+ Figure 7.8
+
+
+13. The **Edit Layout** screen displays the page as shown in Figure 7.9. The circuit is placed inside a back box. The **LAYOUT** panel displays different options for editing the layout of the circuit.
+
+ 
+
+
+ Figure 7.9
+
+
+14. Change the desired settings of the **LAYOUT** panel.
+
+15. Click **Save** to save the layout settings as shown in Figure 7.10.
+
+ 
+
+
+ Figure 7.10
+
+
+## Insert Subcircuit
+
+Subcircuits can be nested across other circuit tabs as a CV simulation or as a Verilog module. This section lists the different steps for inserting subcircuits generated as a CV simulation or as a Verilog code.
+
+### a. Insert Subcircuit as a CircuitVerse Simulation
+
+Follow the below steps for building a full adder circuit using two half-adder subcircuits:
+
+16. Click on the add tab icon (refer Figure 7.11) displayed in the circuit tab section. Alternatively, you may also click on **NewCircuit+** selection in the **Circuit** drop-down menu. As shown in Figure 7.11, the **Enter circuit name:** pop up window is displayed.
+
+ 
+
+
+ Figure 7.11
+
+
+17. Enter a circuit name in the text field as shown in Figure 7.11.
+
+18. Click **OK** to save the circuit name. Refer Figure 7.12.
+
+ 
+
+
+ Figure 7.12
+
+
+19. Navigate to **Circuit** drop-down menu to select **Insert SubCircuit** from the drop down menu. As shown in Figure 7.13, the **Insert SubCircuit** pop up window is displayed.
+
+
+
+
+
+ Figure 7.13
+
+
+20. Select the circuit that you wish to insert. Refer Figure 7.14.
+
+
+
+
+
+ Figure 7.14
+
+
+21. Click the **Insert SubCircuit** button to insert the subcircuit within the **Full Adder** tab (refer Figure 7.14).
+
+22. Repeat the steps from 15 to 20 to add more sub-circuits to your circuit.
+
+ > TIP: Duplicate any circuit by selecting the circuit (CTRL + A), copy the circuit (CTRL + C) and paste the circuit (CTRL + V) in the desired tab or another project file.
+
+23. Refer to Figure 7.15 and complete the wiring connections of the full adder circuit.
+
+ 
+
+
+
+ Figure 7.15
+
+
+### b. Insert Circuit Using Verilog Module
+
+If required, a user can also insert a Verilog module as a subcircuit. Follow the below steps to insert a circuit layout constructed using a verilog module:
+
+1. Navigate to **Circuit** drop-down menu to select **New Verilog Module** from the drop down menu. As shown in Figure 7.16, the **Enter circuit name** pop up window is displayed.
+
+ 
+
+
+ Figure 7.16
+
+
+2. Enter a circuit tab name in the text field. Refer Figure 7.16.
+
+3. Click **OK **to launch the Verilog code interface window as shown in Figure 7.17.
+
+ 
+
+
+ Figure 7.17
+
+
+4. Enter the desired Verilog code in the module interface. Refer Figure 7.18.
+
+ 
+
+
+ Figure 7.18
+
+
+5. Click on the **Save Code** button to receive the message that the code has been saved successfully. Refer Figure 7.19.
+
+ 
+
+
+ Figure 7.19
+
+
+## Annotate Circuit
+
+Follow the below steps to annotate the final circuit diagram:
+
+24. Navigate to the **Misc** section of the **CIRCUIT ELEMENTS** panel as shown in Figure 7.20.
+
+ 
+
+
+ Figure 7.20
+
+
+25. Drag the **Text Tool** element on the canvas as shown in Figure 7.21.
+
+ 
+
+
+ Figure 7.21
+
+
+26. Navigate to the **PROPERTIES** panel to edit the **Label:** text field as shown in Figure 7.21.
+
+27. Repeat steps 24 to 26 to add more annotation elements. In Figure 7.22, a **Rectangle Tool** element has been added to highlight the structural relationship across different elements .
+
+ 
+
+
+ Figure 7.22
+
diff --git a/CircuitVerse-Documentation/docs/chapter7/3testcircuits.mdx b/CircuitVerse-Documentation/docs/chapter7/3testcircuits.mdx
new file mode 100644
index 00000000..e54a05ec
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter7/3testcircuits.mdx
@@ -0,0 +1,60 @@
+---
+id: chapter7-testcircuits
+title: "Testcircuits"
+description: "Testcircuits page in Chapter7 of CircuitVerse documentation."
+---
+
+# Testing CircuitVerse circuits
+
+The Testbench helps you test your circuits in the simulator itself
+
+### It's here in this corner
+
+
+
+### Attach a test to a circuit
+
+Each circuit in a project can be attached a test, this test is saved along with your circuits. So the next time you load your circuit, the test loads with it.
+
+
+
+### Create the test using the test creator
+
+The test creator provides an intuitive UI to create tests.
+
+- Select the type of test - `Sequential` or `Combinational`
+- Add inputs / outputs by clicking the `+` icon next to `INPUTS` / `OUTPUTS` label.
+- Add another test to the group by clicking `+` icon below
+- Add another group by clicking `New Group`
+
+For sequential tests, clock is ticked between each Group. For combinational tests, Groups are just a logical seperation between different types of tests.
+
+Alternatively, you can also export the created test as CSV and edit it. You can import this CSV to attch by clicking `Import from CSV`
+
+Finally,
+
+- Save and attach the test by clicking `Attach`
+
+
+
+### Label your circuit elements
+
+The testbench uses the element labels to identify Input and Output elements. So make sure they are labelled the same as that in the tests.
+
+Click `Validate` to make sure you have added all elements properly
+
+
+
+### Ready to go!
+
+Click the arrows next to Group / Test number to scroll through and run tests
+
+
+
+Click `Run All` to run all the tests in an instant
+
+
+
+And get detailed results!
+
+
diff --git a/CircuitVerse-Documentation/docs/chapter8/1onlineforums.mdx b/CircuitVerse-Documentation/docs/chapter8/1onlineforums.mdx
new file mode 100644
index 00000000..4fba7ec1
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter8/1onlineforums.mdx
@@ -0,0 +1,12 @@
+---
+id: chapter8-onlineforums
+title: "Onlineforums"
+description: "Onlineforums page in Chapter8 of CircuitVerse documentation."
+---
+
+# Online Forums
+
+- CircuitVerse Forum: [https://circuitverse.org/forum](https://circuitverse.org/forum)
+- CircuitVerse on GitHub: [https://github.com/CircuitVerse](https://github.com/CircuitVerse)
+- CircuitVerse on Slack: [https://circuitverse-team.slack.com](https://circuitverse-team.slack.com)
+- CircuitVerse YouTube Channel: [https://www.youtube.com/channel/UCAK48dCPc_QON6Y5QqqRLOg](https://www.youtube.com/channel/UCAK48dCPc_QON6Y5QqqRLOg)
diff --git a/CircuitVerse-Documentation/docs/chapter8/2cvfaq.mdx b/CircuitVerse-Documentation/docs/chapter8/2cvfaq.mdx
new file mode 100644
index 00000000..1f205f44
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter8/2cvfaq.mdx
@@ -0,0 +1,64 @@
+---
+id: chapter8-cvfaq
+title: "Cvfaq"
+description: "Cvfaq page in Chapter8 of CircuitVerse documentation."
+---
+
+# CircuitVerse FAQ
+
+1. What is CircuitVerse?
+
+ CircuitVerse is a free, cloud-based platform for building digital circuit simulations on the go. Watch this video to learn more about the CircuitVerse platform.
+ Figure 8.1
+
+
+8. I'm getting lots of problems with the new UI now. Is the old CircuitVerse simulator interface still accessible?
+
+ While we encourage our users to use the new UI, the old user interface can be accessed from the **Project** drop-down menu in the menu bar. Refer Figure 8.2 for more details.
+
+ 
+
+
+ Figure 8.2
+
diff --git a/CircuitVerse-Documentation/docs/chapter8/3cverrormessages.mdx b/CircuitVerse-Documentation/docs/chapter8/3cverrormessages.mdx
new file mode 100644
index 00000000..b8cdf1da
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter8/3cverrormessages.mdx
@@ -0,0 +1,21 @@
+---
+id: chapter8-cverrormessages
+title: "Cverrormessages"
+description: "Cverrormessages page in Chapter8 of CircuitVerse documentation."
+---
+
+# Understanding Error Messages
+
+1. **Bit Width Error X and Y**: If a wire connects two components demanding different bit widths (one input pin is placing X bits on the wire and another end of the wire is placing a Y bit), the multi-bit wire turns red or black while displaying this message on the simulator.
+
+**Resolution:** Adjust the bit width value of the circuit elements on either end of the wire to establish compatibility of the bit widths.
+
+2. **Stimulation stack limit exceeded**: May be due to cyclic paths or contention.
+
+**Resolution**: Cyclic paths cause an infinite loop and the circuit never reaches a stable state. Sometimes contention in wires presents itself as a cyclic path. Revise your circuit design for circuit nodes that sometimes behave as inputs and sometimes behave as outputs. Alternatively, troubleshoot and resolve the bug in the circuit.
+
+2. **Contention Error 1 and 0**: When the circuit is driven by two or more outputs of both HIGH and LOW, the simulator may display this error.
+
+ 
+
+**Resolution:** Logic contention errors indicate a circuit design problem leading to large amounts of power to flow across circuit elements. Revisit your design for some wiring errors or for active multiple output enable lines that are driving a bus or circuit node simultaneously.
diff --git a/CircuitVerse-Documentation/docs/chapter8/4shortcuts.mdx b/CircuitVerse-Documentation/docs/chapter8/4shortcuts.mdx
new file mode 100644
index 00000000..23688ec5
--- /dev/null
+++ b/CircuitVerse-Documentation/docs/chapter8/4shortcuts.mdx
@@ -0,0 +1,32 @@
+---
+id: chapter8-shortcuts
+title: "Shortcuts"
+description: "Shortcuts page in Chapter8 of CircuitVerse documentation."
+---
+
+# Keyboard Shortcuts
+
+| Keys | Actions |
+| ------------------------------- | :----------------------: |
+| Copy | Ctrl + c |
+| Cut | Ctrl + x |
+| Paste | Ctrl + v |
+| Undo | Ctrl + z |
+| Redo | Ctrl + y |
+| Delete Object(s) | Delete |
+| Select All | Ctrl + a |
+| De-select | ESC |
+| Deattach objects before placing | Backspace |
+| Multi-object Select | Ctrl + scoll using mouse |
+| Save Project Online | Ctrl + s |
+| Save Project Offline | Ctrl + Shift + s |
+| Open Project | Ctrl + o |
+| Download Image | Ctrl + d |
+| Zoom in | Ctrl + '+' |
+| Zoom out | Ctrl + '-' |
+| Enter Time in diagram | T |
+| Make object looks Right | Arrow Right |
+| Make object looks Left | Arrow Left |
+| Make object looks Up | Arrow Up |
+| Make object looks Down | Arrow Down |
+| Open Documentation Page | F1 |
diff --git a/CircuitVerse-Documentation/docusaurus.config.js b/CircuitVerse-Documentation/docusaurus.config.js
new file mode 100644
index 00000000..8c326e1c
--- /dev/null
+++ b/CircuitVerse-Documentation/docusaurus.config.js
@@ -0,0 +1,124 @@
+// @ts-check
+import { themes as prismThemes } from 'prism-react-renderer';
+
+/** @type {import('@docusaurus/types').Config} */
+const config = {
+ title: 'CircuitVerse Documentation',
+ tagline: 'Explore Digital Circuits Online',
+ favicon: 'img/favicon.ico',
+
+ url: 'https://circuitverse-docs.netlify.app/', // Netlify production URL
+ baseUrl: '/',
+
+ organizationName: 'CircuitVerse',
+ projectName: 'CircuitVerseDocs',
+
+ onBrokenLinks: 'throw',
+ onBrokenMarkdownLinks: 'warn',
+
+ i18n: {
+ defaultLocale: 'en',
+ locales: ['en'],
+ },
+
+ presets: [
+ [
+ 'classic',
+ {
+ docs: {
+ sidebarPath: require.resolve('./sidebars.js'),
+ editUrl: 'https://github.com/CircuitVerse/CircuitVerseDocs/edit/main/docs/',
+ routeBasePath: '/',
+ },
+ blog: false, // Disable blog
+ theme: {
+ customCss: [
+ require.resolve('./src/css/theme.css'),
+ require.resolve('./src/css/darkTheme.css'),
+ ],
+ },
+ },
+ ],
+ ],
+
+ themeConfig: {
+ image: 'img/favicon.ico',
+ navbar: {
+ title: 'CircuitVerse Docs',
+ logo: {
+ alt: 'CircuitVerse Logo',
+ src: 'img/favicon.ico',
+ },
+ items: [
+ {
+ type: 'doc',
+ docId: 'chapter1/chapter1-introduction', // Points to Introduction as root
+ position: 'left',
+ label: 'Documentation',
+ },
+ {
+ href: 'https://circuitverse.org',
+ label: 'CircuitVerse Home',
+ position: 'left',
+ },
+ {
+ href: 'https://github.com/CircuitVerse/CircuitVerseDocs',
+ label: 'GitHub',
+ position: 'right',
+ },
+ ],
+ },
+ footer: {
+ style: 'dark',
+ links: [
+ {
+ title: 'Docs',
+ items: [
+ { label: 'Introduction', to: '/' },
+ { label: 'Getting Started', to: '/chapter2/chapter2-gettingstarted' },
+ ],
+ },
+ {
+ title: 'Community',
+ items: [
+ { label: 'CircuitVerse Forum', href: 'https://circuitverse.org/forum' },
+ {
+ label: 'GitHub Discussions',
+ href: 'https://github.com/orgs/CircuitVerse/discussions',
+ },
+ ],
+ },
+ {
+ title: 'More',
+ items: [
+ { label: 'GitHub', href: 'https://github.com/CircuitVerse' },
+ {
+ label: 'YouTube',
+ href: 'https://www.youtube.com/channel/UCAK48dCPc_QON6Y5QqqRLOg',
+ },
+ ],
+ },
+ ],
+ copyright: `Copyright © ${new Date().getFullYear()} CircuitVerse. Built with Docusaurus.`,
+ },
+ prism: {
+ theme: prismThemes.github,
+ darkTheme: prismThemes.dracula,
+ additionalLanguages: ['javascript', 'python', 'css'],
+ },
+ colorMode: {
+ defaultMode: 'light',
+ disableSwitch: false,
+ respectPrefersColorScheme: true,
+ },
+ algolia: {
+ appId: 'DM4KWCC17E',
+ apiKey: '39b1e358bb863804871f81fba53b8f1d',
+ indexName: 'circuitverse-netlify',
+ contextualSearch: true,
+ searchParameters: {}, // Optional: Additional Algolia search parameters
+ },
+ },
+};
+
+export default config;
diff --git a/CircuitVerse-Documentation/package-lock.json b/CircuitVerse-Documentation/package-lock.json
new file mode 100644
index 00000000..ad30205d
--- /dev/null
+++ b/CircuitVerse-Documentation/package-lock.json
@@ -0,0 +1,17351 @@
+{
+ "name": "circuitverse-docs",
+ "version": "0.0.0",
+ "lockfileVersion": 3,
+ "requires": true,
+ "packages": {
+ "": {
+ "name": "circuitverse-docs",
+ "version": "0.0.0",
+ "dependencies": {
+ "@docusaurus/core": "3.6.1",
+ "@docusaurus/preset-classic": "3.6.1",
+ "@easyops-cn/docusaurus-search-local": "^0.45.0",
+ "@mdx-js/react": "^3.0.0",
+ "clsx": "^2.0.0",
+ "prism-react-renderer": "^2.4.0",
+ "react": "^18.0.0",
+ "react-dom": "^18.0.0"
+ },
+ "devDependencies": {
+ "@docusaurus/module-type-aliases": "3.6.1",
+ "@docusaurus/types": "3.6.1",
+ "@types/htmlparser2": "^3.10.7",
+ "eslint": "^8.57.1",
+ "eslint-plugin-mdx": "^3.1.5",
+ "htmlparser2": "^9.1.0"
+ },
+ "engines": {
+ "node": ">=18.0"
+ }
+ },
+ "node_modules/@algolia/autocomplete-core": {
+ "version": "1.17.7",
+ "resolved": "https://registry.npmjs.org/@algolia/autocomplete-core/-/autocomplete-core-1.17.7.tgz",
+ "integrity": "sha512-BjiPOW6ks90UKl7TwMv7oNQMnzU+t/wk9mgIDi6b1tXpUek7MW0lbNOUHpvam9pe3lVCf4xPFT+lK7s+e+fs7Q==",
+ "dependencies": {
+ "@algolia/autocomplete-plugin-algolia-insights": "1.17.7",
+ "@algolia/autocomplete-shared": "1.17.7"
+ }
+ },
+ "node_modules/@algolia/autocomplete-plugin-algolia-insights": {
+ "version": "1.17.7",
+ "resolved": "https://registry.npmjs.org/@algolia/autocomplete-plugin-algolia-insights/-/autocomplete-plugin-algolia-insights-1.17.7.tgz",
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+ "dependencies": {
+ "@algolia/autocomplete-shared": "1.17.7"
+ },
+ "peerDependencies": {
+ "search-insights": ">= 1 < 3"
+ }
+ },
+ "node_modules/@algolia/autocomplete-preset-algolia": {
+ "version": "1.17.7",
+ "resolved": "https://registry.npmjs.org/@algolia/autocomplete-preset-algolia/-/autocomplete-preset-algolia-1.17.7.tgz",
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+ "dependencies": {
+ "@algolia/autocomplete-shared": "1.17.7"
+ },
+ "peerDependencies": {
+ "@algolia/client-search": ">= 4.9.1 < 6",
+ "algoliasearch": ">= 4.9.1 < 6"
+ }
+ },
+ "node_modules/@algolia/autocomplete-shared": {
+ "version": "1.17.7",
+ "resolved": "https://registry.npmjs.org/@algolia/autocomplete-shared/-/autocomplete-shared-1.17.7.tgz",
+ "integrity": "sha512-o/1Vurr42U/qskRSuhBH+VKxMvkkUVTLU6WZQr+L5lGZZLYWyhdzWjW0iGXY7EkwRTjBqvN2EsR81yCTGV/kmg==",
+ "peerDependencies": {
+ "@algolia/client-search": ">= 4.9.1 < 6",
+ "algoliasearch": ">= 4.9.1 < 6"
+ }
+ },
+ "node_modules/@algolia/cache-browser-local-storage": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/cache-browser-local-storage/-/cache-browser-local-storage-4.24.0.tgz",
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+ "dependencies": {
+ "@algolia/cache-common": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/cache-common": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/cache-common/-/cache-common-4.24.0.tgz",
+ "integrity": "sha512-emi+v+DmVLpMGhp0V9q9h5CdkURsNmFC+cOS6uK9ndeJm9J4TiqSvPYVu+THUP8P/S08rxf5x2P+p3CfID0Y4g=="
+ },
+ "node_modules/@algolia/cache-in-memory": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/cache-in-memory/-/cache-in-memory-4.24.0.tgz",
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+ "dependencies": {
+ "@algolia/cache-common": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/client-abtesting": {
+ "version": "5.14.2",
+ "resolved": "https://registry.npmjs.org/@algolia/client-abtesting/-/client-abtesting-5.14.2.tgz",
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+ "dependencies": {
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+ "@algolia/requester-browser-xhr": "5.14.2",
+ "@algolia/requester-fetch": "5.14.2",
+ "@algolia/requester-node-http": "5.14.2"
+ },
+ "engines": {
+ "node": ">= 14.0.0"
+ }
+ },
+ "node_modules/@algolia/client-account": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/client-account/-/client-account-4.24.0.tgz",
+ "integrity": "sha512-adcvyJ3KjPZFDybxlqnf+5KgxJtBjwTPTeyG2aOyoJvx0Y8dUQAEOEVOJ/GBxX0WWNbmaSrhDURMhc+QeevDsA==",
+ "dependencies": {
+ "@algolia/client-common": "4.24.0",
+ "@algolia/client-search": "4.24.0",
+ "@algolia/transporter": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/client-account/node_modules/@algolia/client-common": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/client-common/-/client-common-4.24.0.tgz",
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+ "dependencies": {
+ "@algolia/requester-common": "4.24.0",
+ "@algolia/transporter": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/client-account/node_modules/@algolia/client-search": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/client-search/-/client-search-4.24.0.tgz",
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+ "@algolia/client-common": "4.24.0",
+ "@algolia/requester-common": "4.24.0",
+ "@algolia/transporter": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/client-analytics": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/client-analytics/-/client-analytics-4.24.0.tgz",
+ "integrity": "sha512-y8jOZt1OjwWU4N2qr8G4AxXAzaa8DBvyHTWlHzX/7Me1LX8OayfgHexqrsL4vSBcoMmVw2XnVW9MhL+Y2ZDJXg==",
+ "dependencies": {
+ "@algolia/client-common": "4.24.0",
+ "@algolia/client-search": "4.24.0",
+ "@algolia/requester-common": "4.24.0",
+ "@algolia/transporter": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/client-analytics/node_modules/@algolia/client-common": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/client-common/-/client-common-4.24.0.tgz",
+ "integrity": "sha512-bc2ROsNL6w6rqpl5jj/UywlIYC21TwSSoFHKl01lYirGMW+9Eek6r02Tocg4gZ8HAw3iBvu6XQiM3BEbmEMoiA==",
+ "dependencies": {
+ "@algolia/requester-common": "4.24.0",
+ "@algolia/transporter": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/client-analytics/node_modules/@algolia/client-search": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/client-search/-/client-search-4.24.0.tgz",
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+ "dependencies": {
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+ "@algolia/requester-common": "4.24.0",
+ "@algolia/transporter": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/client-common": {
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+ "engines": {
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+ }
+ },
+ "node_modules/@algolia/client-insights": {
+ "version": "5.14.2",
+ "resolved": "https://registry.npmjs.org/@algolia/client-insights/-/client-insights-5.14.2.tgz",
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+ },
+ "engines": {
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+ }
+ },
+ "node_modules/@algolia/client-personalization": {
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+ "resolved": "https://registry.npmjs.org/@algolia/client-personalization/-/client-personalization-4.24.0.tgz",
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+ }
+ },
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+ "dependencies": {
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+ },
+ "node_modules/@algolia/client-query-suggestions": {
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+ "@algolia/requester-node-http": "5.14.2"
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+ "engines": {
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+ "@algolia/requester-node-http": "5.14.2"
+ },
+ "engines": {
+ "node": ">= 14.0.0"
+ }
+ },
+ "node_modules/@algolia/events": {
+ "version": "4.0.1",
+ "resolved": "https://registry.npmjs.org/@algolia/events/-/events-4.0.1.tgz",
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+ },
+ "node_modules/@algolia/ingestion": {
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+ "@algolia/requester-node-http": "5.14.2"
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+ "engines": {
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+ },
+ "node_modules/@algolia/logger-common": {
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+ "resolved": "https://registry.npmjs.org/@algolia/logger-console/-/logger-console-4.24.0.tgz",
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+ "dependencies": {
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+ }
+ },
+ "node_modules/@algolia/monitoring": {
+ "version": "1.14.2",
+ "resolved": "https://registry.npmjs.org/@algolia/monitoring/-/monitoring-1.14.2.tgz",
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+ "engines": {
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+ }
+ },
+ "node_modules/@algolia/recommend": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/recommend/-/recommend-4.24.0.tgz",
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+ "@algolia/cache-common": "4.24.0",
+ "@algolia/cache-in-memory": "4.24.0",
+ "@algolia/client-common": "4.24.0",
+ "@algolia/client-search": "4.24.0",
+ "@algolia/logger-common": "4.24.0",
+ "@algolia/logger-console": "4.24.0",
+ "@algolia/requester-browser-xhr": "4.24.0",
+ "@algolia/requester-common": "4.24.0",
+ "@algolia/requester-node-http": "4.24.0",
+ "@algolia/transporter": "4.24.0"
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+ },
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+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/client-common/-/client-common-4.24.0.tgz",
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+ "dependencies": {
+ "@algolia/requester-common": "4.24.0",
+ "@algolia/transporter": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/recommend/node_modules/@algolia/client-search": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/client-search/-/client-search-4.24.0.tgz",
+ "integrity": "sha512-uRW6EpNapmLAD0mW47OXqTP8eiIx5F6qN9/x/7HHO6owL3N1IXqydGwW5nhDFBrV+ldouro2W1VX3XlcUXEFCA==",
+ "dependencies": {
+ "@algolia/client-common": "4.24.0",
+ "@algolia/requester-common": "4.24.0",
+ "@algolia/transporter": "4.24.0"
+ }
+ },
+ "node_modules/@algolia/recommend/node_modules/@algolia/requester-browser-xhr": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/requester-browser-xhr/-/requester-browser-xhr-4.24.0.tgz",
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+ "dependencies": {
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+ }
+ },
+ "node_modules/@algolia/recommend/node_modules/@algolia/requester-node-http": {
+ "version": "4.24.0",
+ "resolved": "https://registry.npmjs.org/@algolia/requester-node-http/-/requester-node-http-4.24.0.tgz",
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+ "dependencies": {
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+ },
+ "node_modules/@algolia/requester-browser-xhr": {
+ "version": "5.14.2",
+ "resolved": "https://registry.npmjs.org/@algolia/requester-browser-xhr/-/requester-browser-xhr-5.14.2.tgz",
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+ "dependencies": {
+ "@algolia/client-common": "5.14.2"
+ },
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+}
diff --git a/CircuitVerse-Documentation/package.json b/CircuitVerse-Documentation/package.json
new file mode 100644
index 00000000..69d66c78
--- /dev/null
+++ b/CircuitVerse-Documentation/package.json
@@ -0,0 +1,49 @@
+{
+ "name": "circuitverse-docs",
+ "version": "0.0.0",
+ "private": true,
+ "scripts": {
+ "docusaurus": "docusaurus",
+ "start": "docusaurus start",
+ "build": "docusaurus build",
+ "swizzle": "docusaurus swizzle",
+ "deploy": "docusaurus deploy",
+ "clear": "docusaurus clear",
+ "serve": "docusaurus serve",
+ "write-translations": "docusaurus write-translations",
+ "write-heading-ids": "docusaurus write-heading-ids"
+ },
+ "dependencies": {
+ "@docusaurus/core": "3.6.1",
+ "@docusaurus/preset-classic": "3.6.1",
+ "@easyops-cn/docusaurus-search-local": "^0.45.0",
+ "@mdx-js/react": "^3.0.0",
+ "clsx": "^2.0.0",
+ "prism-react-renderer": "^2.4.0",
+ "react": "^18.0.0",
+ "react-dom": "^18.0.0"
+ },
+ "devDependencies": {
+ "@docusaurus/module-type-aliases": "3.6.1",
+ "@docusaurus/types": "3.6.1",
+ "@types/htmlparser2": "^3.10.7",
+ "eslint": "^8.57.1",
+ "eslint-plugin-mdx": "^3.1.5",
+ "htmlparser2": "^9.1.0"
+ },
+ "browserslist": {
+ "production": [
+ ">0.5%",
+ "not dead",
+ "not op_mini all"
+ ],
+ "development": [
+ "last 3 chrome version",
+ "last 3 firefox version",
+ "last 5 safari version"
+ ]
+ },
+ "engines": {
+ "node": ">=18.0"
+ }
+}
diff --git a/CircuitVerse-Documentation/sidebars.js b/CircuitVerse-Documentation/sidebars.js
new file mode 100644
index 00000000..976afbc3
--- /dev/null
+++ b/CircuitVerse-Documentation/sidebars.js
@@ -0,0 +1,95 @@
+// @ts-check
+
+/**
+ * Creating a sidebar enables you to:
+ * - Create an ordered group of docs
+ * - Render a sidebar for each doc of that group
+ * - Provide next/previous navigation
+ *
+ * The sidebars can be generated from the filesystem, or explicitly defined here.
+ *
+ * @type {import('@docusaurus/plugin-content-docs').SidebarsConfig}
+ */
+const sidebars = {
+ tutorialSidebar: [
+ {
+ type: 'category',
+ label: 'Chapter 1: Introduction',
+ items: [
+ { type: 'doc', id: 'chapter1/chapter1-introduction', label: 'Introduction' },
+ { type: 'doc', id: 'chapter1/chapter1-keyfeatures', label: 'Key Features' },
+ { type: 'doc', id: 'chapter1/chapter1-systemrequirments', label: 'System Requirements' },
+ ],
+ },
+ {
+ type: 'category',
+ label: 'Chapter 2: Getting Started with CircuitVerse',
+ items: [
+ { type: 'doc', id: 'chapter2/chapter2-gettingstarted', label: 'Getting Started' },
+ { type: 'doc', id: 'chapter2/chapter2-cvforeducators', label: 'CircuitVerse For Educators' },
+ { type: 'doc', id: 'chapter2/chapter2-lmsintegration', label: 'Integrate CircuitVerse with LMS' },
+ { type: 'doc', id: 'chapter2/chapter2-ssointegration', label: 'Single Sign-On Configurations' },
+ { type: 'doc', id: 'chapter2/chapter2-bestpracticescv', label: 'Best Practices For Working With CircuitVerse' },
+ ],
+ },
+ {
+ type: 'category',
+ label: 'Chapter 3: Simulator Interface',
+ items: [
+ { type: 'doc', id: 'chapter3/chapter3-introduction', label: 'Introduction' },
+ { type: 'doc', id: 'chapter3/chapter3-understandingcvsimulator', label: 'Understanding CircuitVerse Simulator' },
+ ],
+ },
+ {
+ type: 'category',
+ label: 'Chapter 4: Circuit Elements Library',
+ items: [
+ { type: 'doc', id: 'chapter4/chapter4-introduction', label: 'Introduction' },
+ { type: 'doc', id: 'chapter4/chapter4-input', label: 'Input' },
+ { type: 'doc', id: 'chapter4/chapter4-output', label: 'Output' },
+ { type: 'doc', id: 'chapter4/chapter4-gates', label: 'Gates' },
+ { type: 'doc', id: 'chapter4/chapter4-muxandplex', label: 'Decoders & Plexers' },
+ { type: 'doc', id: 'chapter4/chapter4-sequentialelements', label: 'Sequential Elements' },
+ { type: 'doc', id: 'chapter4/chapter4-annotation', label: 'Annotation' },
+ { type: 'doc', id: 'chapter4/chapter4-misc', label: 'Miscellaneous' },
+ ],
+ },
+ {
+ type: 'category',
+ label: 'Chapter 5: Subcircuits and Edit Layout',
+ items: [
+ { type: 'doc', id: 'chapter5/chapter5-usingsubcircuits', label: 'Using Subcircuits' },
+ { type: 'doc', id: 'chapter5/chapter5-usingeditlayout', label: 'Using Edit Layout' },
+ ],
+ },
+ {
+ type: 'category',
+ label: 'Chapter 6: Timing Diagrams and Delay',
+ items: [
+ { type: 'doc', id: 'chapter6/chapter6-delayvsclock', label: 'Clock Time vs Delay' },
+ { type: 'doc', id: 'chapter6/chapter6-timingdiagram', label: 'Timing Diagram' },
+ ],
+ },
+ {
+ type: 'category',
+ label: 'Chapter 7: Building Circuit Simulations within CircuitVerse',
+ items: [
+ { type: 'doc', id: 'chapter7/chapter7-cvdesignprocess', label: 'CircuitVerse Design Process' },
+ { type: 'doc', id: 'chapter7/chapter7-buildwithcv', label: 'Building Circuit Simulations within CircuitVerse' },
+ { type: 'doc', id: 'chapter7/chapter7-testcircuits', label: 'Testing Circuits' },
+ ],
+ },
+ {
+ type: 'category',
+ label: 'Chapter 8: Support Resources',
+ items: [
+ { type: 'doc', id: 'chapter8/chapter8-onlineforums', label: 'Online Forums' },
+ { type: 'doc', id: 'chapter8/chapter8-cvfaq', label: 'FAQ' },
+ { type: 'doc', id: 'chapter8/chapter8-cverrormessages', label: 'Understanding Error Messages' },
+ { type: 'doc', id: 'chapter8/chapter8-shortcuts', label: 'Keyboard Shortcuts' },
+ ],
+ },
+ ],
+};
+
+export default sidebars;
\ No newline at end of file
diff --git a/CircuitVerse-Documentation/src/css/darkTheme.css b/CircuitVerse-Documentation/src/css/darkTheme.css
new file mode 100644
index 00000000..de2e3199
--- /dev/null
+++ b/CircuitVerse-Documentation/src/css/darkTheme.css
@@ -0,0 +1,3 @@
+.markdown-section td {
+ background: #3F3F3F;
+}
diff --git a/CircuitVerse-Documentation/src/css/theme.css b/CircuitVerse-Documentation/src/css/theme.css
new file mode 100644
index 00000000..2c94c0bb
--- /dev/null
+++ b/CircuitVerse-Documentation/src/css/theme.css
@@ -0,0 +1,107 @@
+.switch {
+ position: relative;
+ display: inline-block;
+ width: 50px;
+ height: 25px;
+ margin-left: 15px;
+ margin-top: 30px;
+ float: right;
+}
+
+/* Hide default HTML checkbox */
+.switch input {
+ opacity: 0;
+ width: 0;
+ height: 0;
+}
+
+/* The slider */
+.slider {
+ position: absolute;
+ cursor: pointer;
+ top: 0;
+ left: 0;
+ right: 0;
+ bottom: 0;
+ background-color: #ccc;
+}
+
+.smooth{
+ -webkit-transition: .4s;
+ transition: .4s;
+}
+
+.slider:before {
+ position: absolute;
+ content: "";
+ height: 16px;
+ width: 16px;
+ left: 4px;
+ bottom: 4px;
+ background-color: white;
+}
+
+.slider.smooth:before {
+ position: absolute;
+ content: "";
+ height: 16px;
+ width: 16px;
+ left: 4px;
+ bottom: 4px;
+ background-color: white;
+ -webkit-transition: .4s;
+ transition: .4s;
+}
+
+input:checked + .slider {
+ background-color: #00bc8c;
+}
+
+input:focus + .slider {
+ box-shadow: 0 0 1px #2196F3;
+}
+
+input:checked + .slider:before {
+ -webkit-transform: translateX(26px);
+ -ms-transform: translateX(26px);
+ transform: translateX(26px);
+}
+
+div[style="overflow: auto"]{
+ margin-top: 15px;
+}
+
+/* Rounded sliders */
+.slider.round {
+ border-radius: 34px;
+}
+
+.slider.round:before {
+ border-radius: 50%;
+}
+
+.sidebar-toggle {
+ bottom: initial;
+}
+
+.search {
+ margin-top: 39px;
+ position: sticky;
+ top: 36px;
+ width: 100%;
+ padding: 0 !important;
+}
+.search .input-wrap {
+ margin-left: 10px;
+}
+.search .results-panel.show {
+ padding: 10px;
+}
+@media (max-width: 768px) {
+ .switch {
+ margin-right: 5%;
+ }
+ body.close .sidebar-toggle{
+ width: 296px;
+ }
+}
diff --git a/CircuitVerse-Documentation/static/.nojekyll b/CircuitVerse-Documentation/static/.nojekyll
new file mode 100644
index 00000000..e69de29b
diff --git a/CircuitVerse-Documentation/static/img/cvlogo.svg b/CircuitVerse-Documentation/static/img/cvlogo.svg
new file mode 100644
index 00000000..27202ecb
--- /dev/null
+++ b/CircuitVerse-Documentation/static/img/cvlogo.svg
@@ -0,0 +1 @@
+