From 80b32836ec2069e537685a6d3dfced7d3afd42ab Mon Sep 17 00:00:00 2001
From: Franz Fuchs <franz.fuchs@cl.cam.ac.uk>
Date: Fri, 19 Apr 2024 08:53:54 +0100
Subject: [PATCH] Added TIDC registers

---
 src/cheri_insts.sail    | 5 +++++
 src/cheri_regs.sail     | 2 ++
 src/cheri_scr_map.sail  | 2 ++
 src/cheri_sys_regs.sail | 2 ++
 4 files changed, 11 insertions(+)

diff --git a/src/cheri_insts.sail b/src/cheri_insts.sail
index e093b641..c7a48072 100644
--- a/src/cheri_insts.sail
+++ b/src/cheri_insts.sail
@@ -364,10 +364,12 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = {
   let (specialExists, ro, priv, needASR) : (bool, bool, Privilege, bool) = match unsigned(scr) {
     0  => (true, true,  User, false),
     1  => (true, false, User, false),
+    3 if haveUsrMode() => (true, true, User, false),
     4 if haveNExt() => (true, false, User, true),
     5 if haveNExt() => (true, false, User, true),
     6 if haveNExt() => (true, false, User, true),
     7 if haveNExt() => (true, false, User, true),
+    11 if haveSupMode() => (true, false, Supervisor, true),
     12 if haveSupMode() => (true, false, Supervisor, true),
     13 if haveSupMode() => (true, false, Supervisor, true),
     14 if haveSupMode() => (true, false, Supervisor, true),
@@ -395,10 +397,12 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = {
         pcc
       },
       1  => DDC,
+      3  => STIDC,
       4  => UTCC,
       5  => UTDC,
       6  => UScratchC,
       7  => legalize_epcc(UEPCC),
+      11 => STIDC,
       12 => STCC,
       13 => STDC,
       14 => SScratchC,
@@ -416,6 +420,7 @@ function clause execute (CSpecialRW(cd, scr, cs1)) = {
         5  => UTDC = cs1_val,
         6  => UScratchC = cs1_val,
         7  => UEPCC = cs1_val,
+        12 => STIDC = cs1_val,
         12 => STCC = legalize_tcc(STCC, cs1_val),
         13 => STDC = cs1_val,
         14 => SScratchC = cs1_val,
diff --git a/src/cheri_regs.sail b/src/cheri_regs.sail
index 57b09d80..a684bcf2 100644
--- a/src/cheri_regs.sail
+++ b/src/cheri_regs.sail
@@ -159,11 +159,13 @@ function ext_init_regs () = {
   DDC = default_cap;
   nextPCC = default_cap;
 
+  UTIDC = null_cap;
   UTCC = default_cap;
   UTDC = null_cap;
   UScratchC = null_cap;
   UEPCC = default_cap;
 
+  STIDC = null_cap;
   STCC = default_cap;
   STDC = null_cap;
   SScratchC = null_cap;
diff --git a/src/cheri_scr_map.sail b/src/cheri_scr_map.sail
index 042f85ac..3a5d701b 100644
--- a/src/cheri_scr_map.sail
+++ b/src/cheri_scr_map.sail
@@ -69,11 +69,13 @@ scattered mapping scr_name_map
 mapping clause scr_name_map = 0b00000 <-> "pcc"
 mapping clause scr_name_map = 0b00001 <-> "ddc"
 
+mapping clause scr_name_map = 0b00011 <-> "utidc"
 mapping clause scr_name_map = 0b00100 <-> "utcc"
 mapping clause scr_name_map = 0b00101 <-> "utdc"
 mapping clause scr_name_map = 0b00110 <-> "uscratchc"
 mapping clause scr_name_map = 0b00111 <-> "uepcc"
 
+mapping clause scr_name_map = 0b01011 <-> "stidc"
 mapping clause scr_name_map = 0b10100 <-> "stcc"
 mapping clause scr_name_map = 0b10101 <-> "stdc"
 mapping clause scr_name_map = 0b10110 <-> "sscratchc"
diff --git a/src/cheri_sys_regs.sail b/src/cheri_sys_regs.sail
index 3b871168..e68bdd63 100644
--- a/src/cheri_sys_regs.sail
+++ b/src/cheri_sys_regs.sail
@@ -114,10 +114,12 @@ register PCC       : Capability
 register nextPCC   : Capability
 register DDC       : Capability
 
+register UTIDC     : Capability
 register UTCC      : Capability
 register UTDC      : Capability
 register UScratchC : Capability
 register UEPCC     : Capability
+register STIDC     : Capability
 register STCC      : Capability
 register STDC      : Capability
 register SScratchC : Capability